sdk/fidl/fuchsia.hardware.registers/register-util.fidl

// Copyright 2020 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
library fuchsia.hardware.registers;

using zx;

closed protocol Device {
    /// Reads from the register from the specified MMIO offset in register width equal to 8, 16, 32, and
    /// 64 bit variants.
    /// |offset| : Offset from base of MMIO to read from. Offset must be aligned to beginning of register. For
    ///             example, for 32 bits, offset must be divisible by 4, and for 64 bits, offset
    ///             must be divisible by 8. If this is not satisfied, read will fail.
    /// |mask| : Mask of bits to read. For example, to read the lower 2 bytes of data in a 32 bit
    ///          register, mask should be 0x0000FFFF.
    /// @Returns: |value| : Value of register at the specified address.
    strict ReadRegister8(struct {
        offset uint64;
        mask uint8;
    }) -> (struct {
        value uint8;
    }) error zx.Status;
    strict ReadRegister16(struct {
        offset uint64;
        mask uint16;
    }) -> (struct {
        value uint16;
    }) error zx.Status;
    strict ReadRegister32(struct {
        offset uint64;
        mask uint32;
    }) -> (struct {
        value uint32;
    }) error zx.Status;
    strict ReadRegister64(struct {
        offset uint64;
        mask uint64;
    }) -> (struct {
        value uint64;
    }) error zx.Status;

    /// Writes to the register at the specified MMIO offset in register width equal to 8, 16, 32, and
    /// 64 bit variants
    /// |offset| : Offset from base of MMIO to write to. Offset must be aligned to beginning of register. For
    ///             example, for 32 bits, offset must be divisible by 4, and for 64 bits, offset
    ///             must be divisible by 8. If this is not satisfied, write will fail.
    /// |mask| : Mask of bits to write. For example, to write to the lower 2 bytes of data in a 32
    ///          bit register, mask should be 0x0000FFFF.
    /// |value| : Value of register at the specified address.
    strict WriteRegister8(struct {
        offset uint64;
        mask uint8;
        value uint8;
    }) -> () error zx.Status;
    strict WriteRegister16(struct {
        offset uint64;
        mask uint16;
        value uint16;
    }) -> () error zx.Status;
    strict WriteRegister32(struct {
        offset uint64;
        mask uint32;
        value uint32;
    }) -> () error zx.Status;
    strict WriteRegister64(struct {
        offset uint64;
        mask uint64;
        value uint64;
    }) -> () error zx.Status;
};

service Service {
    device client_end:Device;
};