sdk/fidl/fuchsia.hardware.clockimpl/init.fidl

// Copyright 2023 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

library fuchsia.hardware.clockimpl;

using zx;

type EnableType = struct {};
type DisableType = struct {};

/// A fuchsia.hardware.clock.Clock call to make as part of an `InitStep`.
type InitCall = flexible union {
    /// If set, the clock core driver will call `Enable`.
    1: enable EnableType;
    /// If set, the clock core driver will call `Disable`.
    2: disable DisableType;
    /// If set, the clock core driver will call `SetRate` with the given frequency in Hertz.
    3: rate_hz uint64;
    /// If set, the clock core driver will call `SetInput` with the given input index.
    4: input_idx uint32;
    /// If set, the clock core driver will delay for this long before processing the next step.
    5: delay zx.Duration;
};

/// A single init step to be performed by the clock core driver.
type InitStep = table {
    /// The platform-specific clock ID that this step operates on.
    /// This must be unset if `call` is of type `InitCall::delay` and must be set otherwise.
    1: id uint32;

    /// A call to make on this clock. This must be set.
    2: call InitCall;
};

/// Passed to the clock core driver in metadata. Steps are processed sequentially in the order that
/// they appear in the vector. Processing occurs once during the clock core driver's bind hook.
@serializable
type InitMetadata = struct {
    steps vector<InitStep>:MAX;
};