sdk/fidl/fuchsia.hardware.amlogic.metadata/spi.fidl

// Copyright 2025 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
library fuchsia.hardware.amlogic.metadata;

const CS_CLIENT_MANAGED uint32 = 0xffffffff;
const DEFAULT_DELAY_CONTROL uint32 = 0x15;
const MAX_CS_COUNT uint32 = 4;

@serializable
type SpiConfig = struct {
    bus_id uint32;

    /// The index of the GPIO to use for each SPI device. GPIOs are expected to be fragments named
    /// "gpio-cs-n", where n is the valued stored in `cs`.
    /// Alternatively, entries may be set to `CS_CLIENT_MANAGED` to indicate that the client driver
    /// will manage the cs GPIO for this chip (or that cs isn't needed).
    cs vector<uint32>:MAX_CS_COUNT;

    /// The clock divider register value (NOT the actual clock divider) to use for SCLK.
    /// If `use_enhanced_clock_mode` is true:
    ///     - `clock_divider_register_value` is written to ENHANCE_CNTL, and must be in [0, 255].
    ///     - The bus clock frequency is: core clock / (2 * (`clock_divider_register_value` + 1))
    /// If `use_enhanced_clock_mode` is false:
    ///     - `clock_divider_register_value` is written to CONREG, and must be in [0, 7].
    ///     - The bus clock frequency is: core clock / (2 ^ (`clock_divider_register_value` + 2))
    clock_divider_register_value uint32;

    /// If true, the SPI driver uses the enhanced clock mode instead of the regular clock mode.
    use_enhanced_clock_mode bool;

    /// If true, the client is responsible for reversing the endianness of transfers when using DMA.
    client_reverses_dma_transfers bool;

    /// The value to use for the dlyctl field in TESTREG. The default value should work for
    /// low-speed peripherals.
    delay_control uint32;
};