[kernel] Remove old CPUID topology code
This code is no longer in use (and there are no projected usages for
which the current pace of the CpuidIo migration would present a
problem).
Bug: 61093
Change-Id: I0a11f1efb04b587e464f94cc2ae954a316baa483
Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/474478
Fuchsia-Auto-Submit: Joshua Seaton <joshuaseaton@google.com>
Commit-Queue: Auto-Submit <auto-submit@fuchsia-infra.iam.gserviceaccount.com>
Reviewed-by: Venkatesh Srinivas <venkateshs@google.com>
diff --git a/zircon/kernel/arch/x86/cpuid/cpuid.cc b/zircon/kernel/arch/x86/cpuid/cpuid.cc
index d2758ee..8bab802 100644
--- a/zircon/kernel/arch/x86/cpuid/cpuid.cc
+++ b/zircon/kernel/arch/x86/cpuid/cpuid.cc
@@ -36,47 +36,6 @@
return result;
}
-// Convert power of two value to a shift_width.
-uint8_t ToShiftWidth(uint32_t value) { return static_cast<uint8_t>(log2_uint_ceil(value)); }
-
-Registers FindHighestCacheSubleaf(uint32_t leaf) {
- Registers empty = {};
-
- // Check to see if these are valid leaves for this processor.
- Registers max_leaf = CallCpuId((leaf < ExtendedLeaf<0>()) ? 0 : ExtendedLeaf<0>());
- if (leaf > max_leaf.eax()) {
- // Out of range, return an empty value.
- return empty;
- }
-
- ktl::optional<Registers> highest;
- const uint32_t max_cache_levels = 32;
- for (uint32_t i = 0; i < max_cache_levels; i++) {
- const Registers current = CallCpuId(leaf, i);
- LTRACEF("leaf %#x %#x: %#x %#x %#x %#x\n", leaf, i, current.eax(), current.ebx(), current.ecx(),
- current.edx());
- if ((current.eax() & 0xF) == 0) { // Null level
- // If we encounter a null level the last level should be the highest.
-
- // If there is no highest just return an empty value.
- if (!highest) {
- return empty;
- }
- return *highest;
- }
-
- // We want to find the numerically highest cache level.
- if (!highest || ((*highest).eax() & 0xFF) < (current.eax() & 0xFF)) {
- highest = {current};
- }
- }
-
- printf("WARNING: more than %u levels of cache, couldn't find highest on leaf %#x\n",
- max_cache_levels, leaf);
-
- return highest.value_or(empty);
-}
-
} // namespace
ManufacturerInfo CpuId::ReadManufacturerInfo() const {
@@ -90,14 +49,6 @@
CallCpuId(ExtendedLeaf<7>()), CallCpuId(ExtendedLeaf<8>()));
}
-Topology CpuId::ReadTopology() const {
- SubLeaves<Topology::kEaxBSubleaves> leafB = {CallCpuId(0xB, 0), CallCpuId(0xB, 1),
- CallCpuId(0xB, 2)};
- return Topology(ReadManufacturerInfo(), ReadFeatures(), FindHighestCacheSubleaf(4), leafB,
- CallCpuId(ExtendedLeaf<8>()), FindHighestCacheSubleaf(ExtendedLeaf<0x1D>()),
- CallCpuId(ExtendedLeaf<0x1E>()));
-}
-
ManufacturerInfo::ManufacturerInfo(Registers leaf0, Registers leaf8_0)
: leaf0_(leaf0), leaf8_0_(leaf8_0) {}
@@ -166,180 +117,4 @@
return fbl::ExtractBits<23, 16, uint8_t>(leaves_[LEAF1].ebx());
}
-Topology::Topology(ManufacturerInfo info, Features features, Registers leaf4,
- SubLeaves<kEaxBSubleaves> leafB, Registers leaf8_8, Registers leaf8_1D,
- Registers leaf8_1E)
- : info_(info),
- features_(features),
- leaf4_(leaf4),
- leafB_(leafB),
- leaf8_8_(leaf8_8),
- leaf8_1D_(leaf8_1D),
- leaf8_1E_(leaf8_1E) {}
-
-ktl::optional<Topology::Levels> Topology::IntelLevels() const {
- Topology::Levels levels;
- if (info_.highest_cpuid_leaf() >= 11) {
- int nodes_under_previous_level = 0;
- int bits_in_previous_levels = 0;
- for (int i = 0; i < 3; i++) {
- const uint8_t width = fbl::ExtractBits<4, 0, uint8_t>(leafB_.subleaf[i].eax());
- if (width) {
- uint8_t raw_type = fbl::ExtractBits<15, 8, uint8_t>(leafB_.subleaf[i].ecx());
-
- LevelType type = LevelType::INVALID;
- if (raw_type == 1) {
- type = LevelType::SMT;
- } else if (raw_type == 2) {
- type = LevelType::CORE;
- } else if (i == 2) {
- // Package is defined as the "last" level.
- type = LevelType::DIE;
- }
-
- // This actually contains total logical processors in all
- // subtrees of this level of the topology.
- const uint16_t nodes_under_level = fbl::ExtractBits<7, 0, uint8_t>(leafB_.subleaf[i].ebx());
- const uint8_t node_count = static_cast<uint8_t>(
- nodes_under_level /
- ((nodes_under_previous_level == 0) ? 1 : nodes_under_previous_level));
- const uint8_t id_bits = static_cast<uint8_t>(width - bits_in_previous_levels);
-
- levels.levels[levels.level_count++] = {
- .type = type,
- // Dividing by logical processors under last level will give
- // us the nodes that are at this level.
- .node_count = node_count,
- .id_bits = id_bits,
- };
- nodes_under_previous_level += nodes_under_level;
- bits_in_previous_levels += id_bits;
- }
- }
- } else if (info_.highest_cpuid_leaf() >= 4) {
- const bool single_core = !features_.HasFeature(Features::HTT);
- if (single_core) {
- levels.levels[levels.level_count++] = {
- .type = LevelType::DIE,
- .node_count = 1,
- .id_bits = 0,
- };
- } else {
- const auto logical_in_package = features_.max_logical_processors_in_package();
- const auto cores_in_package = fbl::ExtractBits<31, 26, uint8_t>(leaf4_.eax()) + 1;
- const auto logical_per_core = logical_in_package / cores_in_package;
- if (logical_per_core > 1) {
- levels.levels[levels.level_count++] = {
- .type = LevelType::SMT,
- .id_bits = ToShiftWidth(logical_per_core),
- };
- }
-
- if (cores_in_package > 1) {
- levels.levels[levels.level_count++] = {
- .type = LevelType::CORE,
- .id_bits = ToShiftWidth(cores_in_package),
- };
- }
- }
- } else {
- // If this is an intel CPU then cpuid leaves are disabled on the system
- // IA32_MISC_ENABLES[22] == 1. This can be set to 0, usually in the BIOS,
- // the kernel can change it too but we prefer to stay read-only here.
- printf(
- "WARNING: Unable to parse topology, missing necessary ACPI leaves. "
- "They may be disabled in the bios.\n");
- return ktl::nullopt;
- }
-
- return (levels.level_count == 0) ? ktl::nullopt : ktl::make_optional(levels);
-}
-
-ktl::optional<Topology::Levels> Topology::AmdLevels() const {
- Topology::Levels levels;
- if (info_.highest_extended_cpuid_leaf() >= ExtendedLeaf<8>()) {
- uint8_t thread_id_bits = fbl::ExtractBits<15, 12, uint8_t>(leaf8_8_.ecx());
- if (thread_id_bits == 0) {
- thread_id_bits =
- static_cast<uint8_t>(log2_uint_ceil(fbl::ExtractBits<7, 0, uint8_t>(leaf8_8_.ecx()) + 1));
- }
-
- const uint8_t smt_bits =
- static_cast<uint8_t>(log2_uint_ceil(fbl::ExtractBits<15, 8, uint8_t>(leaf8_1E_.ebx()) + 1));
-
- const uint8_t node_bits =
- static_cast<uint8_t>(log2_uint_ceil(fbl::ExtractBits<10, 8, uint8_t>(leaf8_1E_.ecx()) + 1));
-
- // thread_id is the unique id of a thread in a package (socket), if we
- // remove the bits used to identify the thread inside of the core (smt)
- // and the bits used to idenfity to which node the core belongs, what is
- // left should be the bits used to id the core?
- const uint8_t core_bits = static_cast<uint8_t>(thread_id_bits - smt_bits - node_bits);
-
- if (smt_bits) {
- levels.levels[levels.level_count++] = {
- .type = LevelType::SMT,
- .id_bits = smt_bits,
- };
- }
-
- if (core_bits) {
- levels.levels[levels.level_count++] = {
- .type = LevelType::CORE,
- .id_bits = core_bits,
- };
- }
-
- if (node_bits) {
- levels.levels[levels.level_count++] = {
- .type = LevelType::DIE, // NODE in AMD parlance seems to equate to a die.
- .id_bits = node_bits,
- };
- }
-
- } else {
- const uint8_t core_bits =
- static_cast<uint8_t>(log2_uint_ceil(features_.max_logical_processors_in_package()));
- levels.levels[levels.level_count++] = {
- .type = LevelType::CORE,
- .id_bits = ToShiftWidth(core_bits),
- };
- }
-
- return (levels.level_count == 0) ? ktl::nullopt : ktl::make_optional(levels);
-}
-
-ktl::optional<Topology::Levels> Topology::levels() const {
- auto levels = IntelLevels();
- if (levels) {
- return levels;
- }
-
- // If Intel approach didn't work try the AMD approach, even on AMD chips the
- // intel approach may work, there are hypervisor cases that populate it.
- levels = AmdLevels();
- if (levels) {
- return levels;
- }
-
- printf(
- "WARNING: Unable to parse topology from CPUID. If this is an Intel chip, "
- "ensure IA32_MISC_ENABLES[22] is off.\n");
- return ktl::nullopt;
-}
-
-Topology::Cache Topology::highest_level_cache() const {
- const auto& leaf = (leaf4_.eax() != 0) ? leaf4_ /*Intel*/ : leaf8_1D_ /*AMD*/;
- const uint16_t threads_sharing_cache =
- static_cast<uint16_t>(fbl::ExtractBits<25, 14, uint16_t>(leaf.eax()) + 1);
- LTRACEF("threads sharing cache %u\n", threads_sharing_cache);
- return {
- .level = fbl::ExtractBits<7, 5, uint8_t>(leaf.eax()),
- .shift_width = ToShiftWidth(threads_sharing_cache),
- .size_bytes = (fbl::ExtractBits<31, 22, uint16_t>(leaf.ebx()) + 1) *
- (fbl::ExtractBits<21, 12, uint16_t>(leaf.ebx()) + 1) *
- (fbl::ExtractBits<11, 0, uint16_t>(leaf.ebx()) + 1) * (leaf.ecx() + 1),
- };
-}
-
} // namespace cpu_id
diff --git a/zircon/kernel/arch/x86/cpuid/cpuid_test.cc b/zircon/kernel/arch/x86/cpuid/cpuid_test.cc
index 7fca043..3a39c24 100644
--- a/zircon/kernel/arch/x86/cpuid/cpuid_test.cc
+++ b/zircon/kernel/arch/x86/cpuid/cpuid_test.cc
@@ -20,7 +20,6 @@
using cpu_id::ManufacturerInfo;
using cpu_id::ProcessorId;
using cpu_id::Registers;
-using cpu_id::Topology;
} // namespace
@@ -182,106 +181,6 @@
END_TEST;
}
-bool test_intel_topology() {
- BEGIN_TEST;
- auto topology = cpu_id::kCpuIdXeon2690v4.ReadTopology();
-
- const auto levels_opt = topology.levels();
- ASSERT_TRUE(levels_opt);
-
- const auto& levels = *levels_opt;
- EXPECT_EQ(Topology::LevelType::SMT, levels.levels[0].type);
- EXPECT_EQ(2u, levels.levels[0].node_count);
- EXPECT_EQ(1u, levels.levels[0].id_bits);
-
- EXPECT_EQ(Topology::LevelType::CORE, levels.levels[1].type);
- EXPECT_EQ(14u, levels.levels[1].node_count);
- EXPECT_EQ(4u, levels.levels[1].id_bits);
-
- EXPECT_EQ(Topology::LevelType::INVALID, levels.levels[2].type);
-
- END_TEST;
-}
-
-// Tests other intel path, using leaf4 instead of extended leafB.
-bool test_intel_topology_leaf4() {
- BEGIN_TEST;
- auto data = cpu_id::kTestDataXeon2690v4;
-
- // We need to report that we don't support leafB.
- auto modifiedLeaf0 = data.leaf0;
- modifiedLeaf0.reg[Registers::EAX] = 4;
- auto manufacturer = ManufacturerInfo(modifiedLeaf0, data.leaf8_0);
- EXPECT_EQ(4u, manufacturer.highest_cpuid_leaf());
-
- Topology topology(manufacturer,
- Features(data.leaf1, data.leaf6, data.leaf7, data.leaf8_1, data.leaf8_7,
- data.leaf8_8),
- data.leaf4, data.leafB, data.leaf8_8, data.leaf8_1D, data.leaf8_1E);
-
- const auto levels_opt = topology.levels();
- ASSERT_TRUE(levels_opt);
-
- const auto& levels = *levels_opt;
- ASSERT_EQ(Topology::LevelType::SMT, levels.levels[0].type);
- EXPECT_EQ(Topology::kInvalidCount, levels.levels[0].node_count);
- EXPECT_EQ(1u, levels.levels[0].id_bits);
-
- ASSERT_EQ(Topology::LevelType::CORE, levels.levels[1].type);
- EXPECT_EQ(Topology::kInvalidCount, levels.levels[1].node_count);
- EXPECT_EQ(4u, levels.levels[1].id_bits);
-
- EXPECT_EQ(Topology::LevelType::INVALID, levels.levels[2].type);
-
- END_TEST;
-}
-
-bool test_amd_topology() {
- BEGIN_TEST;
- auto topology = cpu_id::kCpuIdThreadRipper2970wx.ReadTopology();
-
- const auto levels_opt = topology.levels();
- ASSERT_TRUE(levels_opt);
-
- const auto& levels = *levels_opt;
- ASSERT_EQ(Topology::LevelType::SMT, levels.levels[0].type);
- EXPECT_EQ(1u, levels.levels[0].id_bits);
-
- ASSERT_EQ(Topology::LevelType::CORE, levels.levels[1].type);
- EXPECT_EQ(3u, levels.levels[1].id_bits);
-
- ASSERT_EQ(Topology::LevelType::DIE, levels.levels[2].type);
- EXPECT_EQ(2u, levels.levels[2].id_bits);
-
- END_TEST;
-}
-
-bool test_intel_highest_cache() {
- BEGIN_TEST;
- auto topology = cpu_id::kCpuIdXeon2690v4.ReadTopology();
-
- const auto cache = topology.highest_level_cache();
-
- EXPECT_EQ(3u, cache.level);
- EXPECT_EQ(5u, cache.shift_width);
- EXPECT_EQ(35u << 20 /*35 megabytes*/, cache.size_bytes);
-
- END_TEST;
-}
-
-bool test_amd_highest_cache() {
- BEGIN_TEST;
- auto topology = cpu_id::kCpuIdThreadRipper2970wx.ReadTopology();
-
- const auto cache = topology.highest_level_cache();
-
- EXPECT_EQ(3u, cache.level);
- EXPECT_EQ(3u, cache.shift_width);
- EXPECT_EQ(8u << 20 /*8 megabytes*/, cache.size_bytes);
-
- END_TEST;
-}
-
UNITTEST_START_TESTCASE(cpuid_tests)
UNITTEST("Parse feature flags from static Intel data.", test_intel_feature_flags)
UNITTEST("Parse feature flags from static AMD data.", test_amd_feature_flags)
@@ -292,9 +191,4 @@
UNITTEST("Parse manufacturer info from AMD static data.", test_amd_manufacturer_info)
UNITTEST("Parse processor id from Intel static data.", test_intel_processor_id)
UNITTEST("Parse processor id from AMD static data.", test_amd_processor_id)
-UNITTEST("Parse topology from static Intel data.", test_intel_topology)
-UNITTEST("Parse topology from static data, using leaf4.", test_intel_topology_leaf4)
-UNITTEST("Parse topology from static AMD data.", test_amd_topology)
-UNITTEST("Parse cache information from static Intel data.", test_intel_highest_cache)
-UNITTEST("Parse cache information from static AMD data.", test_amd_highest_cache)
UNITTEST_END_TESTCASE(cpuid_tests, "cpuid", "Test parsing of cpuid values.")
diff --git a/zircon/kernel/arch/x86/cpuid/include/arch/x86/cpuid.h b/zircon/kernel/arch/x86/cpuid/include/arch/x86/cpuid.h
index 0ee1c40..bd544bc 100644
--- a/zircon/kernel/arch/x86/cpuid/include/arch/x86/cpuid.h
+++ b/zircon/kernel/arch/x86/cpuid/include/arch/x86/cpuid.h
@@ -282,77 +282,6 @@
const Registers leaves_[kLeafCount];
};
-// Parses topology data from the CPUID instruction.
-class Topology {
- public:
- static constexpr size_t kEaxBSubleaves = 3;
- static constexpr size_t kMaxLevels = 3;
- static constexpr uint8_t kInvalidCount = 255;
-
- enum class LevelType {
- INVALID,
- SMT,
- CORE,
- DIE,
- };
- struct Level {
- LevelType type = LevelType::INVALID;
-
- // node_count is set best-effort, only some systems provide it.
- uint8_t node_count = kInvalidCount;
-
- // This many bits of the apic id are used to distinguish different nodes in this level.
- // In other words, the width by which you would need to shift an apic id to "skip"
- // this level.
- uint8_t id_bits = 0;
- };
- struct Levels {
- Level levels[kMaxLevels];
- uint8_t level_count = 0;
- };
-
- struct Cache {
- uint8_t level = 0;
-
- // This is how many bits you need to shift the apic id right by in order
- // to determine which cache is serving it.
- uint8_t shift_width = 0;
-
- uint64_t size_bytes = 0;
- };
-
- // Leaf4 and 8_1D being provided should represent the highest level of cache.
- // Intel labels leaf 4 as "Deterministic Cache Parameters" and leaf 0xB as
- // "Processor Topology".
- Topology(ManufacturerInfo info, Features features, Registers leaf4,
- SubLeaves<kEaxBSubleaves> leafB, Registers leaf8_1, Registers leaf8_1D,
- Registers leaf8_1E);
-
- // Provides details for each level of this system's topology.
- // Returns nullopt if unable to parse topology from cpuid data.
- ktl::optional<Levels> levels() const;
-
- // Returns info about the numerically highest level (i.e. L3 > L2 > L1) of processor cache.
- Cache highest_level_cache() const;
-
- protected:
- // Used for testing.
- Topology() : info_({}, {}), features_({}, {}, {}, {}, {}, {}) {}
-
- private:
- ktl::optional<Levels> IntelLevels() const;
- ktl::optional<Levels> AmdLevels() const;
-
- ManufacturerInfo info_;
- Features features_;
-
- Registers leaf4_;
- SubLeaves<kEaxBSubleaves> leafB_;
- Registers leaf8_8_;
- Registers leaf8_1D_;
- Registers leaf8_1E_;
-};
-
// Wraps the CPUID instruction on x86, provides helpers to parse the output and
// allows unit testing of libraries reading it.
// CpuId is uncached; every call results in one (or more) invocations of CPUID.
@@ -363,7 +292,6 @@
// Return ProcessorId; provides (Extended) Family/Model/Stepping.
virtual ProcessorId ReadProcessorId() const;
virtual Features ReadFeatures() const;
- virtual Topology ReadTopology() const;
private:
};
diff --git a/zircon/kernel/arch/x86/cpuid/include/arch/x86/cpuid_test_data.h b/zircon/kernel/arch/x86/cpuid/include/arch/x86/cpuid_test_data.h
index 90266c4a..d40278f 100644
--- a/zircon/kernel/arch/x86/cpuid/include/arch/x86/cpuid_test_data.h
+++ b/zircon/kernel/arch/x86/cpuid/include/arch/x86/cpuid_test_data.h
@@ -4,6 +4,9 @@
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/MIT
+#ifndef ZIRCON_KERNEL_ARCH_X86_CPUID_INCLUDE_ARCH_X86_CPUID_TEST_DATA_H_
+#define ZIRCON_KERNEL_ARCH_X86_CPUID_INCLUDE_ARCH_X86_CPUID_TEST_DATA_H_
+
#include <arch/x86/cpuid.h>
namespace cpu_id {
@@ -16,7 +19,6 @@
Registers leaf4;
Registers leaf6;
Registers leaf7;
- SubLeaves<Topology::kEaxBSubleaves> leafB;
Registers leaf8_0;
Registers leaf8_1;
Registers leaf8_7;
@@ -47,9 +49,6 @@
.leaf4 = {.reg = {0x1c004121, 0x1c0003f, 0x3f, 0x0}},
.leaf6 = {.reg = {0x4f7, 0x2, 0x9, 0x0}},
.leaf7 = {.reg = {0x0, 0x29c67af, 0x0, 0x9c002400}},
- .leafB = {{{.reg = {0x1, 0x2, 0x100, 0x0}},
- {.reg = {0x4, 0x4, 0x201, 0x0}},
- {.reg = {0x0, 0x0, 0x2, 0x0}}}},
.leaf8_0 = {.reg = {0x80000008, 0x0, 0x0, 0x0}},
.leaf8_1 = {.reg = {0x0, 0x0, 0x121, 0x2c100800}},
.leaf8_7 = {},
@@ -84,9 +83,6 @@
.leaf4 = {.reg = {0x3C07C163, 0x4C0003F, 0x6FFF, 0x6}},
.leaf6 = {},
.leaf7 = {.reg = {0x0, 0x21CBFBB, 0x0, 0x9C000000}},
- .leafB = {{{.reg = {0x1, 0x2, 0x100, 0x28}},
- {.reg = {0x5, 0x1C, 0x201, 0x29}},
- {.reg = {0x0, 0x0, 0x2, 0x38}}}},
.leaf8_0 = {.reg = {0x80000008, 0x0, 0x0, 0x0}},
.leaf8_1 = {.reg = {0x0, 0x0, 0x121, 0x2C100800}},
.leaf8_7 = {},
@@ -115,12 +111,9 @@
.leaf4 = {.reg = {0x0, 0x0, 0x0, 0x0}},
.leaf6 = {},
.leaf7 = {.reg = {0x0, 0x209C01A9, 0x0, 0x0}},
- .leafB = {{{.reg = {0x0, 0x0, 0x0, 0x0}},
- {.reg = {0x0, 0x0, 0x0, 0x0}},
- {.reg = {0x0, 0x0, 0x0, 0x0}}}},
.leaf8_0 = {.reg = {0x8000001F, 0x68747541, 0x444D4163, 0x69746E65}},
.leaf8_1 = {.reg = {0x800F82, 0x70000000, 0x35C233FF, 0x2FD3FBFF}},
- .leaf8_7 = {.reg = {0x0, 0x1b, 0x0, 0x6799}},
+ .leaf8_7 = {.reg = {0x0, 0x1b, 0x0, 0x6799}},
.leaf8_8 = {.reg = {0x3030, 0x1007, 0x602F, 0x0}},
.leaf8_1D = {.reg = {0x14163, 0x3C0003F, 0x1FFF, 0x1}},
.leaf8_1E = {.reg = {0x34, 0x102, 0x303, 0x0}},
@@ -144,9 +137,6 @@
.leaf4 = {.reg = {0x0, 0x0, 0x0, 0x0}},
.leaf6 = {.reg = {0x0, 0x0, 0x1, 0x0}},
.leaf7 = {.reg = {0x0, 0x1a9, 0x0, 0x0}},
- .leafB = {{{.reg = {0x0, 0x0, 0x0, 0x0}},
- {.reg = {0x0, 0x0, 0x0, 0x0}},
- {.reg = {0x0, 0x0, 0x0, 0x0}}}},
.leaf8_0 = {.reg = {0x8000001e, 0x68747541, 0x444d4163, 0x69746e65}},
.leaf8_1 = {.reg = {0x670f00, 0x40000000, 0x2fabbfff, 0x2fd3fbff}},
.leaf8_7 = {.reg = {0x0, 0x5, 0x400, 0x37d9}},
@@ -164,7 +154,6 @@
.leaf4 = {.reg = {0x3c000121, 0x140003f, 0x3f, 0x1}},
.leaf6 = {},
.leaf7 = {.reg = {0x0, 0x2294e283, 0x0, 0x2c000000}},
- .leafB = {},
.leaf8_0 = {.reg = {0x80000008, 0x0, 0x0, 0x0}},
.leaf8_1 = {.reg = {0x0, 0x0, 0x101, 0x2c100800}},
.leaf8_7 = {},
@@ -188,13 +177,6 @@
data_.leaf8_8);
}
- Topology ReadTopology() const override {
- return Topology(ManufacturerInfo(data_.leaf0, data_.leaf8_0),
- Features(data_.leaf1, data_.leaf6, data_.leaf7, data_.leaf8_1, data_.leaf8_7,
- data_.leaf8_8),
- data_.leaf4, data_.leafB, data_.leaf8_8, data_.leaf8_1D, data_.leaf8_1E);
- }
-
private:
const TestDataSet& data_;
};
@@ -206,3 +188,5 @@
const FakeCpuId kCpuIdCeleronJ3455(kTestDataCeleronJ3455);
} // namespace cpu_id
+
+#endif // ZIRCON_KERNEL_ARCH_X86_CPUID_INCLUDE_ARCH_X86_CPUID_TEST_DATA_H_
diff --git a/zircon/kernel/arch/x86/feature.cc b/zircon/kernel/arch/x86/feature.cc
index e50ffd8..fb0213c 100644
--- a/zircon/kernel/arch/x86/feature.cc
+++ b/zircon/kernel/arch/x86/feature.cc
@@ -350,22 +350,6 @@
return true;
}
-bool x86_topology_enumerate(uint8_t level, struct x86_topology_level* info) {
- DEBUG_ASSERT(info);
-
- uint32_t eax, ebx, ecx, edx;
- cpuid_c(X86_CPUID_TOPOLOGY, level, &eax, &ebx, &ecx, &edx);
-
- uint8_t type = (ecx >> 8) & 0xff;
- if (type == X86_TOPOLOGY_INVALID) {
- return false;
- }
-
- info->right_shift = eax & 0x1f;
- info->type = type;
- return true;
-}
-
const struct x86_model_info* x86_get_model(void) { return &model_info; }
void x86_feature_debug(void) {
diff --git a/zircon/kernel/arch/x86/include/arch/x86/feature.h b/zircon/kernel/arch/x86/include/arch/x86/feature.h
index 25fc34c..3a8545f 100644
--- a/zircon/kernel/arch/x86/include/arch/x86/feature.h
+++ b/zircon/kernel/arch/x86/include/arch/x86/feature.h
@@ -241,34 +241,6 @@
extern enum x86_vendor_list x86_vendor;
-/* topology */
-
-#define X86_TOPOLOGY_INVALID 0
-#define X86_TOPOLOGY_SMT 1
-#define X86_TOPOLOGY_CORE 2
-
-struct x86_topology_level {
- /* The number of bits to right shift to identify the next-higher topological
- * level */
- uint8_t right_shift;
- /* The type of relationship this level describes (hyperthread/core/etc) */
- uint8_t type;
-};
-
-/**
- * @brief Fetch the topology information for the given level.
- *
- * This interface is uncached.
- *
- * @param level The level to retrieve info for. Should initially be 0 and
- * incremented with each call.
- * @param info The structure to populate with the discovered information
- *
- * @return true if the requested level existed (and there may be higher levels).
- * @return false if the requested level does not exist (and no higher ones do).
- */
-bool x86_topology_enumerate(uint8_t level, struct x86_topology_level* info);
-
struct x86_model_info {
uint8_t processor_type;
uint8_t family;
