- // MIR for `otherwise_t4_unreachable_default` before UnreachableEnumBranching | |
+ // MIR for `otherwise_t4_unreachable_default` after UnreachableEnumBranching | |
fn otherwise_t4_unreachable_default() -> () { | |
let mut _0: (); | |
let _1: &str; | |
let mut _2: Test4; | |
let mut _3: isize; | |
let _4: &str; | |
let _5: &str; | |
let _6: &str; | |
bb0: { | |
StorageLive(_1); | |
StorageLive(_2); | |
_2 = Test4::C; | |
_3 = discriminant(_2); | |
- switchInt(move _3) -> [0: bb4, 1: bb3, 2: bb2, otherwise: bb1]; | |
+ switchInt(move _3) -> [0: bb4, 1: bb3, 2: bb2, 3: bb1, otherwise: bb6]; | |
} | |
bb1: { | |
StorageLive(_6); | |
_6 = const "D"; | |
_1 = &(*_6); | |
StorageDead(_6); | |
goto -> bb5; | |
} | |
bb2: { | |
StorageLive(_5); | |
_5 = const "C"; | |
_1 = &(*_5); | |
StorageDead(_5); | |
goto -> bb5; | |
} | |
bb3: { | |
StorageLive(_4); | |
_4 = const "B(i32)"; | |
_1 = &(*_4); | |
StorageDead(_4); | |
goto -> bb5; | |
} | |
bb4: { | |
_1 = const "A(i32)"; | |
goto -> bb5; | |
} | |
bb5: { | |
StorageDead(_2); | |
StorageDead(_1); | |
_0 = const (); | |
return; | |
+ } | |
+ | |
+ bb6: { | |
+ unreachable; | |
} | |
} | |