sdk/fidl/fuchsia.hardware.vreg/vreg.fidl

// Copyright 2023 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
library fuchsia.hardware.vreg;

using zx;

@discoverable
closed protocol Vreg {
    // Set the step which yields a voltage of min_uv + step_size_uv * step.
    strict SetVoltageStep(struct {
        step uint32;
    }) -> () error zx.Status;

    // Get the current step.
    strict GetVoltageStep() -> (struct {
        result uint32;
    });

    // Obtain the parameters for this voltage regulator.
    // The output for this voltage regulator is defined by the
    // following formula:
    //
    //  v_out = min_voltage + step_size * step
    //
    // Where the `step` is programmable by software.
    strict GetRegulatorParams() -> (struct {
        // Minimum voltage supported by this voltage regulator.
        min_uv uint32;

        // Voltage increment at each step.
        step_size_uv uint32;

        // Max number of steps.
        num_steps uint32;
    });
};

service Service {
    vreg client_end:Vreg;
};