src/tests/benchmarks/fidl/reference/BUILD.gn

# Copyright 2020 The Fuchsia Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.

import("//build/components.gni")
import("//src/tests/benchmarks/fidl/benchmark_suite/benchmark_suite.gni")
import("//tools/fidl/gidl/gidl.gni")

gidl_reference_benchmarks("benchmark_suite_reference") {
  testonly = true
  inputs = [
    "//src/tests/benchmarks/fidl/benchmark_suite/byte_vector.gen.gidl",
    "//src/tests/benchmarks/fidl/benchmark_suite/padded_struct_tree.gen.gidl",
    "//src/tests/benchmarks/fidl/benchmark_suite/struct_tree.gen.gidl",
    "//src/tests/benchmarks/fidl/benchmark_suite/table_all_set.gen.gidl",
    "//src/tests/benchmarks/fidl/benchmark_suite/table_all_unset.gen.gidl",
    "//src/tests/benchmarks/fidl/benchmark_suite/table_single_set.gen.gidl",
  ]
  fidl = benchmark_suite_fidl_target
  deps = [ "//zircon/system/ulib/fidl" ]
}

executable("bin") {
  output_name = "reference_fidl_microbenchmarks"
  testonly = true
  sources = [
    "byte_vector.cc",
    "main.cc",
    "padded_struct_tree.cc",
    "struct_tree.cc",

    # TODO(fxbug.dev/84116) Re-enable once v2 wire format migration is complete.
    #"uint8_table.cc",
  ]
  deps = [
    ":benchmark_suite_reference",
    "//src/zircon/lib/zircon",
    "//zircon/system/ulib/fidl",
    "//zircon/system/ulib/perftest",
    "//zircon/system/ulib/sync",
  ]
}

fuchsia_shell_package("reference") {
  testonly = true
  deps = [ ":bin" ]
}