src/devices/bind/fuchsia.amlogic.platform.meson/fuchsia.amlogic.platform.meson.bind

// Copyright 2021 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

library fuchsia.amlogic.platform.meson;

// Values taken from <soc/aml-meson/g12a-clk.h>
uint G12A_CLK_ID {
  // Meson Gate clocks
  CLK_SYS_PLL_DIV16 = 65536,
  CLK_DOS = 65539,
  CLK_DOS_GCLK_VDEC = 65602,
  CLK_SYS_CPU_CLK_DIV16 = 65537,

  // CPU clocks
  CLK_SYS_CPU_CLK = 1048576,
};

// Values taken from <soc/aml-meson/g12b-clk.h>
uint G12B_CLK_ID {
  // SYS CPU Clocks
  CLK_SYS_PLL_DIV16 = 65536,
  CLK_SYS_CPU_CLK_DIV16 = 65537,

  // GPIO 24MHz
  CLK_CAM_INCK_24M = 65538,

  // SYS CPUB Clocks
  CLK_SYS_PLLB_DIV16 = 65539,
  CLK_SYS_CPUB_CLK_DIV16 = 65540,

  CLK_DOS_GCLK_VDEC = 65541,
  CLK_DOS_GCLK_HCODEC = 65542,
  CLK_DOS = 65543,

  // CPU Clocks
  CLK_SYS_CPU_BIG_CLK = 1048576,
  CLK_SYS_CPU_LITTLE_CLK = 1048577,
};

// Values taken from <soc/aml-meson/sm1-clk.h>
uint SM1_CLK_ID {
  CLK_SYS_PLL_DIV16 = 0x10000,
  CLK_SYS_CPU_CLK_DIV16 = 0x10001,
  CLK_DOS_GCLK_VDEC = 0x10049,
  CLK_DOS = 0x10003,
};

// Values taken from <soc/aml-meson/axg-clk.h>
uint AXG_CLK_ID {
  CLK_DOS_GCLK_VDEC = 0x1002e,
  CLK_AXG_DOS = 0x1002f,
};

// Values taken from <soc/aml-meson/a5-clk.h>
uint A5_CLK_ID {
  CLK_NAND_SEL = 0x4000b,
  CLK_PWM_G = 0x1001f,
};