tools/fidl/fidlgen_llcpp/codegen/file_wire_types_header.tmpl

{{/*
// Copyright 2021 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
*/}}

{{- define "Filename:WireTypesHeader" -}}
fidl/{{ .LibraryDots }}/cpp/wire_types.h
{{- end }}


{{- define "File:WireTypesHeader" -}}
  {{- UseWire -}}
  // WARNING: This file is machine generated by fidlgen.

  #pragma once

  #include <cinttypes>

  #include <lib/fidl/llcpp/array.h>
  #include <lib/fidl/llcpp/coding.h>
  #include <lib/fidl/llcpp/envelope.h>
  #include <lib/fidl/llcpp/message_storage.h>
  #include <lib/fidl/llcpp/message.h>
  #include <lib/fidl/llcpp/object_view.h>
  #include <lib/fidl/llcpp/string_view.h>
  #include <lib/fidl/llcpp/traits.h>
  #include <lib/fidl/llcpp/wire_types.h>
  #include <lib/stdcompat/optional.h>
  {{- IfdefFuchsia -}}
    {{ range .HandleTypes -}}
      #include <{{ . }}>
    {{ end -}}
    {{ if .ContainsDriverReferences -}}
    #include <lib/fidl_driver/cpp/wire_types.h>
    {{ end -}}
  {{- EndifFuchsia }}

  #include <{{ .Library | Filename "Markers" }}>
  #include <{{ .Library | Filename "CommonTypesHeader" }}>
  {{ range .Dependencies -}}
    #include <{{ . | Filename "WireTypesHeader" }}>
  {{ end }}

  {{ range .Bits }}{{ template "Bits:WireTypesHeader" . }}{{ end }}
  {{ range .Enums }}{{ template "Enum:WireTypesHeader" . }}{{ end }}
  {{ range .Structs }}{{ template "Struct:ForwardDeclaration:WireTypesHeader" . }}{{ end }}
  {{ range .Tables }}{{ template "Table:ForwardDeclaration:WireTypesHeader" . }}{{ end }}
  {{ range .Unions }}{{ template "Union:ForwardDeclaration:WireTypesHeader" . }}{{ end }}

  {{- /* Resolve inline object declaration order by defining small inline structs first
    (size <= 4 so can't contain a table or a union), then tables and unions, then
    the remaining types. */}}
  {{- range .Structs }}
    {{ if le .TypeShapeV2.InlineSize 4 }}{{ template "Struct:WireTypesHeader" . }}{{ end }}
  {{- end }}
  {{ range .Tables }}{{ template "Table:WireTypesHeader" . }}{{ end }}
  {{ range .Unions }}{{ template "Union:WireTypesHeader" . }}{{ end }}
  {{ range .Consts }}{{ template "Const:WireTypesHeader" . }}{{ end }}
  {{ range .Structs }}
    {{ if gt .TypeShapeV2.InlineSize 4 }}{{ template "Struct:WireTypesHeader" . }}{{ end }}
  {{- end }}

  {{ EnsureNamespace "fidl" }}

  {{ range .Structs }}{{ template "Struct:Traits:WireTypesHeader" . }}{{ end }}
  {{ range .Tables }}{{ template "Table:Traits:WireTypesHeader" . }}{{ end }}
  {{ range .Unions }}{{ template "Union:Traits:WireTypesHeader" . }}{{ end }}

  {{ EndOfFile }}
{{ end }}