| // Copyright 2018 The Fuchsia Authors. All rights reserved. |
| // Use of this source code is governed by a BSD-style license that can be |
| // found in the LICENSE file. |
| |
| #pragma once |
| |
| |
| |
| /* viu */ |
| #define VPU_VIU_ADDR_START (0x1a00 << 2) |
| #define VPU_VIU_ADDR_END (0x1aff << 2) |
| #define VPU_VIU_SW_RESET (0x1a01 << 2) |
| #define VPU_VIU_SW_RESET0 (0x1a02 << 2) |
| #define VPU_VIU_SECURE_REG (0x1a04 << 2) |
| #define VPU_VIU_MISC_CTRL0 (0x1a06 << 2) |
| #define VPU_VIU_MISC_CTRL1 (0x1a07 << 2) |
| #define VPU_VIU_OSD1_CTRL_STAT (0x1a10 << 2) |
| #define VPU_VIU_OSD1_CTRL_STAT2 (0x1a2d << 2) |
| #define VPU_VIU_OSD1_COLOR_ADDR (0x1a11 << 2) |
| #define VPU_VIU_OSD1_COLOR (0x1a12 << 2) |
| #define VPU_VIU_OSD1_TCOLOR_AG0 (0x1a17 << 2) |
| #define VPU_VIU_OSD1_TCOLOR_AG1 (0x1a18 << 2) |
| #define VPU_VIU_OSD1_TCOLOR_AG2 (0x1a19 << 2) |
| #define VPU_VIU_OSD1_TCOLOR_AG3 (0x1a1a << 2) |
| #define VPU_VIU_OSD1_BLK0_CFG_W0 (0x1a1b << 2) |
| #define VPU_VIU_OSD1_BLK1_CFG_W0 (0x1a1f << 2) |
| #define VPU_VIU_OSD1_BLK2_CFG_W0 (0x1a23 << 2) |
| #define VPU_VIU_OSD1_BLK3_CFG_W0 (0x1a27 << 2) |
| #define VPU_VIU_OSD1_BLK0_CFG_W1 (0x1a1c << 2) |
| #define VPU_VIU_OSD1_BLK1_CFG_W1 (0x1a20 << 2) |
| #define VPU_VIU_OSD1_BLK2_CFG_W1 (0x1a24 << 2) |
| #define VPU_VIU_OSD1_BLK3_CFG_W1 (0x1a28 << 2) |
| #define VPU_VIU_OSD1_BLK0_CFG_W2 (0x1a1d << 2) |
| #define VPU_VIU_OSD1_BLK1_CFG_W2 (0x1a21 << 2) |
| #define VPU_VIU_OSD1_BLK2_CFG_W2 (0x1a25 << 2) |
| #define VPU_VIU_OSD1_BLK3_CFG_W2 (0x1a29 << 2) |
| #define VPU_VIU_OSD1_BLK0_CFG_W3 (0x1a1e << 2) |
| #define VPU_VIU_OSD1_BLK1_CFG_W3 (0x1a22 << 2) |
| #define VPU_VIU_OSD1_BLK2_CFG_W3 (0x1a26 << 2) |
| #define VPU_VIU_OSD1_BLK3_CFG_W3 (0x1a2a << 2) |
| #define VPU_VIU_OSD1_BLK0_CFG_W4 (0x1a13 << 2) |
| #define VPU_VIU_OSD1_BLK1_CFG_W4 (0x1a14 << 2) |
| #define VPU_VIU_OSD1_BLK2_CFG_W4 (0x1a15 << 2) |
| #define VPU_VIU_OSD1_BLK3_CFG_W4 (0x1a16 << 2) |
| #define VPU_VIU_OSD1_FIFO_CTRL_STAT (0x1a2b << 2) |
| #define VPU_VIU_OSD1_TEST_RDDATA (0x1a2c << 2) |
| #define VPU_VIU_OSD1_PROT_CTRL (0x1a2e << 2) |
| #define VPU_VIU_OSD1_MATRIX_CTRL (0x1a90 << 2) |
| #define VPU_VIU_OSD1_MATRIX_COEF00_01 (0x1a91 << 2) |
| #define VPU_VIU_OSD1_MATRIX_COEF02_10 (0x1a92 << 2) |
| #define VPU_VIU_OSD1_MATRIX_COEF11_12 (0x1a93 << 2) |
| #define VPU_VIU_OSD1_MATRIX_COEF20_21 (0x1a94 << 2) |
| #define VPU_VIU_OSD1_MATRIX_COLMOD_COEF42 (0x1a95 << 2) |
| #define VPU_VIU_OSD1_MATRIX_OFFSET0_1 (0x1a96 << 2) |
| #define VPU_VIU_OSD1_MATRIX_OFFSET2 (0x1a97 << 2) |
| #define VPU_VIU_OSD1_MATRIX_PRE_OFFSET0_1 (0x1a98 << 2) |
| #define VPU_VIU_OSD1_MATRIX_PRE_OFFSET2 (0x1a99 << 2) |
| #define VPU_VIU_OSD1_MATRIX_PROBE_COLOR (0x1a9a << 2) |
| #define VPU_VIU_OSD1_MATRIX_HL_COLOR (0x1a9b << 2) |
| #define VPU_VIU_OSD1_MATRIX_PROBE_POS (0x1a9c << 2) |
| #define VPU_VIU_OSD1_MATRIX_COEF22_30 (0x1a9d << 2) |
| #define VPU_VIU_OSD1_MATRIX_COEF31_32 (0x1a9e << 2) |
| #define VPU_VIU_OSD1_MATRIX_COEF40_41 (0x1a9f << 2) |
| #define VPU_VIU_OSD1_EOTF_CTL (0x1ad4 << 2) |
| #define VPU_VIU_OSD1_EOTF_COEF00_01 (0x1ad5 << 2) |
| #define VPU_VIU_OSD1_EOTF_COEF02_10 (0x1ad6 << 2) |
| #define VPU_VIU_OSD1_EOTF_COEF11_12 (0x1ad7 << 2) |
| #define VPU_VIU_OSD1_EOTF_COEF20_21 (0x1ad8 << 2) |
| #define VPU_VIU_OSD1_EOTF_COEF22_RS (0x1ad9 << 2) |
| #define VPU_VIU_OSD1_EOTF_LUT_ADDR_PORT (0x1ada << 2) |
| #define VPU_VIU_OSD1_EOTF_LUT_DATA_PORT (0x1adb << 2) |
| #define VPU_VIU_OSD1_OETF_CTL (0x1adc << 2) |
| #define VPU_VIU_OSD1_OETF_LUT_ADDR_PORT (0x1add << 2) |
| #define VPU_VIU_OSD1_OETF_LUT_DATA_PORT (0x1ade << 2) |
| #define VPU_VIU_OSD1_OETF_3X3_OFST_0 (0x1aa0 << 2) |
| #define VPU_VIU_OSD1_OETF_3X3_OFST_1 (0x1aa1 << 2) |
| #define VPU_VIU_OSD2_CTRL_STAT (0x1a30 << 2) |
| #define VPU_VIU_OSD2_CTRL_STAT2 (0x1a4d << 2) |
| #define VPU_VIU_OSD2_COLOR_ADDR (0x1a31 << 2) |
| #define VPU_VIU_OSD2_COLOR (0x1a32 << 2) |
| #define VPU_VIU_OSD2_HL1_H_START_END (0x1a33 << 2) |
| #define VPU_VIU_OSD2_HL1_V_START_END (0x1a34 << 2) |
| #define VPU_VIU_OSD2_HL2_H_START_END (0x1a35 << 2) |
| #define VPU_VIU_OSD2_HL2_V_START_END (0x1a36 << 2) |
| #define VPU_VIU_OSD2_TCOLOR_AG0 (0x1a37 << 2) |
| #define VPU_VIU_OSD2_TCOLOR_AG1 (0x1a38 << 2) |
| #define VPU_VIU_OSD2_TCOLOR_AG2 (0x1a39 << 2) |
| #define VPU_VIU_OSD2_TCOLOR_AG3 (0x1a3a << 2) |
| #define VPU_VIU_OSD2_BLK0_CFG_W0 (0x1a3b << 2) |
| #define VPU_VIU_OSD2_BLK1_CFG_W0 (0x1a3f << 2) |
| #define VPU_VIU_OSD2_BLK2_CFG_W0 (0x1a43 << 2) |
| #define VPU_VIU_OSD2_BLK3_CFG_W0 (0x1a47 << 2) |
| #define VPU_VIU_OSD2_BLK0_CFG_W1 (0x1a3c << 2) |
| #define VPU_VIU_OSD2_BLK1_CFG_W1 (0x1a40 << 2) |
| #define VPU_VIU_OSD2_BLK2_CFG_W1 (0x1a44 << 2) |
| #define VPU_VIU_OSD2_BLK3_CFG_W1 (0x1a48 << 2) |
| #define VPU_VIU_OSD2_BLK0_CFG_W2 (0x1a3d << 2) |
| #define VPU_VIU_OSD2_BLK1_CFG_W2 (0x1a41 << 2) |
| #define VPU_VIU_OSD2_BLK2_CFG_W2 (0x1a45 << 2) |
| #define VPU_VIU_OSD2_BLK3_CFG_W2 (0x1a49 << 2) |
| #define VPU_VIU_OSD2_BLK0_CFG_W3 (0x1a3e << 2) |
| #define VPU_VIU_OSD2_BLK1_CFG_W3 (0x1a42 << 2) |
| #define VPU_VIU_OSD2_BLK2_CFG_W3 (0x1a46 << 2) |
| #define VPU_VIU_OSD2_BLK3_CFG_W3 (0x1a4a << 2) |
| #define VPU_VIU_OSD2_BLK0_CFG_W4 (0x1a64 << 2) |
| #define VPU_VIU_OSD2_BLK1_CFG_W4 (0x1a65 << 2) |
| #define VPU_VIU_OSD2_BLK2_CFG_W4 (0x1a66 << 2) |
| #define VPU_VIU_OSD2_BLK3_CFG_W4 (0x1a67 << 2) |
| #define VPU_VIU_OSD2_FIFO_CTRL_STAT (0x1a4b << 2) |
| #define VPU_VIU_OSD2_TEST_RDDATA (0x1a4c << 2) |
| #define VPU_VIU_OSD2_PROT_CTRL (0x1a4e << 2) |
| #define VPU_VIU_VD1_FMT_CTRL (0x1a68 << 2) |
| #define VPU_VIU_VD1_FMT_W (0x1a69 << 2) |
| #define VPU_VIU_VD2_FMT_CTRL (0x1a88 << 2) |
| #define VPU_VIU_VD2_FMT_W (0x1a89 << 2) |
| #define VPU_VIU_OSD2_MATRIX_CTRL (0x1ab0 << 2) |
| #define VPU_VIU_OSD2_MATRIX_COEF00_01 (0x1ab1 << 2) |
| #define VPU_VIU_OSD2_MATRIX_COEF02_10 (0x1ab2 << 2) |
| #define VPU_VIU_OSD2_MATRIX_COEF11_12 (0x1ab3 << 2) |
| #define VPU_VIU_OSD2_MATRIX_COEF20_21 (0x1ab4 << 2) |
| #define VPU_VIU_OSD2_MATRIX_COEF22 (0x1ab5 << 2) |
| #define VPU_VIU_OSD2_MATRIX_OFFSET0_1 (0x1ab6 << 2) |
| #define VPU_VIU_OSD2_MATRIX_OFFSET2 (0x1ab7 << 2) |
| #define VPU_VIU_OSD2_MATRIX_PRE_OFFSET0_1 (0x1ab8 << 2) |
| #define VPU_VIU_OSD2_MATRIX_PRE_OFFSET2 (0x1ab9 << 2) |
| #define VPU_VIU_OSD2_MATRIX_PROBE_COLOR (0x1aba << 2) |
| #define VPU_VIU_OSD2_MATRIX_HL_COLOR (0x1abb << 2) |
| #define VPU_VIU_OSD2_MATRIX_PROBE_POS (0x1abc << 2) |
| #define VPU_VIU_RESET (0x0020 << 2) |
| #define VPU_VIU_OSD_BLEND_CTRL (0x39b0 << 2) |
| #define VPU_VIU_OSD_BLEND_CTRL1 (0x39c0 << 2) |
| #define VPU_VIU_OSD_BLEND_DIN0_SCOPE_H (0x39b1 << 2) |
| #define VPU_VIU_OSD_BLEND_DIN0_SCOPE_V (0x39b2 << 2) |
| #define VPU_VIU_OSD_BLEND_DIN1_SCOPE_H (0x39b3 << 2) |
| #define VPU_VIU_OSD_BLEND_DIN1_SCOPE_V (0x39b4 << 2) |
| #define VPU_VIU_OSD_BLEND_DIN2_SCOPE_H (0x39b5 << 2) |
| #define VPU_VIU_OSD_BLEND_DIN2_SCOPE_V (0x39b6 << 2) |
| #define VPU_VIU_OSD_BLEND_DIN3_SCOPE_H (0x39b7 << 2) |
| #define VPU_VIU_OSD_BLEND_DIN3_SCOPE_V (0x39b8 << 2) |
| #define VPU_VIU_OSD_BLEND_DUMMY_DATA0 (0x39b9 << 2) |
| #define VPU_VIU_OSD_BLEND_DUMMY_ALPHA (0x39ba << 2) |
| #define VPU_VIU_OSD_BLEND_BLEND0_SIZE (0x39bb << 2) |
| #define VPU_VIU_OSD_BLEND_BLEND1_SIZE (0x39bc << 2) |
| #define VPU_VIU_OSD_BLEND_RO_CURRENT_XY (0x39bf << 2) |
| |
| /* VPP */ |
| #define VPU_VPP2_DUMMY_DATA (0x1900 << 2) |
| #define VPU_VPP2_LINE_IN_LENGTH (0x1901 << 2) |
| #define VPU_VPP2_PIC_IN_HEIGHT (0x1902 << 2) |
| #define VPU_VPP2_SCALE_COEF_IDX (0x1903 << 2) |
| #define VPU_VPP2_SCALE_COEF (0x1904 << 2) |
| #define VPU_VPP2_VSC_REGION12_STARTP (0x1905 << 2) |
| #define VPU_VPP2_VSC_REGION34_STARTP (0x1906 << 2) |
| #define VPU_VPP2_VSC_REGION4_ENDP (0x1907 << 2) |
| #define VPU_VPP2_VSC_START_PHASE_STEP (0x1908 << 2) |
| #define VPU_VPP2_VSC_REGION0_PHASE_SLOPE (0x1909 << 2) |
| #define VPU_VPP2_VSC_REGION1_PHASE_SLOPE (0x190a << 2) |
| #define VPU_VPP2_VSC_REGION3_PHASE_SLOPE (0x190b << 2) |
| #define VPU_VPP2_VSC_REGION4_PHASE_SLOPE (0x190c << 2) |
| #define VPU_VPP2_VSC_PHASE_CTRL (0x190d << 2) |
| #define VPU_VPP2_VSC_INI_PHASE (0x190e << 2) |
| #define VPU_VPP2_HSC_REGION12_STARTP (0x1910 << 2) |
| #define VPU_VPP2_HSC_REGION34_STARTP (0x1911 << 2) |
| #define VPU_VPP2_HSC_REGION4_ENDP (0x1912 << 2) |
| #define VPU_VPP2_HSC_START_PHASE_STEP (0x1913 << 2) |
| #define VPU_VPP2_HSC_REGION0_PHASE_SLOPE (0x1914 << 2) |
| #define VPU_VPP2_HSC_REGION1_PHASE_SLOPE (0x1915 << 2) |
| #define VPU_VPP2_HSC_REGION3_PHASE_SLOPE (0x1916 << 2) |
| #define VPU_VPP2_HSC_REGION4_PHASE_SLOPE (0x1917 << 2) |
| #define VPU_VPP2_HSC_PHASE_CTRL (0x1918 << 2) |
| #define VPU_VPP2_SC_MISC (0x1919 << 2) |
| #define VPU_VPP2_PREBLEND_VD1_H_START_END (0x191a << 2) |
| #define VPU_VPP2_PREBLEND_VD1_V_START_END (0x191b << 2) |
| #define VPU_VPP2_POSTBLEND_VD1_H_START_END (0x191c << 2) |
| #define VPU_VPP2_POSTBLEND_VD1_V_START_END (0x191d << 2) |
| #define VPU_VPP2_PREBLEND_H_SIZE (0x1920 << 2) |
| #define VPU_VPP2_POSTBLEND_H_SIZE (0x1921 << 2) |
| #define VPU_VPP2_HOLD_LINES (0x1922 << 2) |
| #define VPU_VPP2_BLEND_ONECOLOR_CTRL (0x1923 << 2) |
| #define VPU_VPP2_PREBLEND_CURRENT_XY (0x1924 << 2) |
| #define VPU_VPP2_POSTBLEND_CURRENT_XY (0x1925 << 2) |
| #define VPU_VPP2_MISC (0x1926 << 2) |
| #define VPU_VPP2_OFIFO_SIZE (0x1927 << 2) |
| #define VPU_VPP2_FIFO_STATUS (0x1928 << 2) |
| #define VPU_VPP2_SMOKE_CTRL (0x1929 << 2) |
| #define VPU_VPP2_SMOKE1_VAL (0x192a << 2) |
| #define VPU_VPP2_SMOKE2_VAL (0x192b << 2) |
| #define VPU_VPP2_SMOKE1_H_START_END (0x192d << 2) |
| #define VPU_VPP2_SMOKE1_V_START_END (0x192e << 2) |
| #define VPU_VPP2_SMOKE2_H_START_END (0x192f << 2) |
| #define VPU_VPP2_SMOKE2_V_START_END (0x1930 << 2) |
| #define VPU_VPP2_SCO_FIFO_CTRL (0x1933 << 2) |
| #define VPU_VPP2_HSC_PHASE_CTRL1 (0x1934 << 2) |
| #define VPU_VPP2_HSC_INI_PAT_CTRL (0x1935 << 2) |
| #define VPU_VPP2_VADJ_CTRL (0x1940 << 2) |
| #define VPU_VPP2_VADJ1_Y (0x1941 << 2) |
| #define VPU_VPP2_VADJ1_MA_MB (0x1942 << 2) |
| #define VPU_VPP2_VADJ1_MC_MD (0x1943 << 2) |
| #define VPU_VPP2_VADJ2_Y (0x1944 << 2) |
| #define VPU_VPP2_VADJ2_MA_MB (0x1945 << 2) |
| #define VPU_VPP2_VADJ2_MC_MD (0x1946 << 2) |
| #define VPU_VPP2_MATRIX_PROBE_COLOR (0x195c << 2) |
| #define VPU_VPP2_MATRIX_HL_COLOR (0x195d << 2) |
| #define VPU_VPP2_MATRIX_PROBE_POS (0x195e << 2) |
| #define VPU_VPP2_MATRIX_CTRL (0x195f << 2) |
| #define VPU_VPP2_MATRIX_COEF00_01 (0x1960 << 2) |
| #define VPU_VPP2_MATRIX_COEF02_10 (0x1961 << 2) |
| #define VPU_VPP2_MATRIX_COEF11_12 (0x1962 << 2) |
| #define VPU_VPP2_MATRIX_COEF20_21 (0x1963 << 2) |
| #define VPU_VPP2_MATRIX_COEF22 (0x1964 << 2) |
| #define VPU_VPP2_MATRIX_OFFSET0_1 (0x1965 << 2) |
| #define VPU_VPP2_MATRIX_OFFSET2 (0x1966 << 2) |
| #define VPU_VPP2_MATRIX_PRE_OFFSET0_1 (0x1967 << 2) |
| #define VPU_VPP2_MATRIX_PRE_OFFSET2 (0x1968 << 2) |
| #define VPU_VPP2_DUMMY_DATA1 (0x1969 << 2) |
| #define VPU_VPP2_GAINOFF_CTRL0 (0x196a << 2) |
| #define VPU_VPP2_GAINOFF_CTRL1 (0x196b << 2) |
| #define VPU_VPP2_GAINOFF_CTRL2 (0x196c << 2) |
| #define VPU_VPP2_GAINOFF_CTRL3 (0x196d << 2) |
| #define VPU_VPP2_GAINOFF_CTRL4 (0x196e << 2) |
| #define VPU_VPP2_CHROMA_ADDR_PORT (0x1970 << 2) |
| #define VPU_VPP2_CHROMA_DATA_PORT (0x1971 << 2) |
| #define VPU_VPP2_GCLK_CTRL0 (0x1972 << 2) |
| #define VPU_VPP2_GCLK_CTRL1 (0x1973 << 2) |
| #define VPU_VPP2_SC_GCLK_CTRL (0x1974 << 2) |
| #define VPU_VPP2_MISC1 (0x1976 << 2) |
| #define VPU_VPP2_DNLP_CTRL_00 (0x1981 << 2) |
| #define VPU_VPP2_DNLP_CTRL_01 (0x1982 << 2) |
| #define VPU_VPP2_DNLP_CTRL_02 (0x1983 << 2) |
| #define VPU_VPP2_DNLP_CTRL_03 (0x1984 << 2) |
| #define VPU_VPP2_DNLP_CTRL_04 (0x1985 << 2) |
| #define VPU_VPP2_DNLP_CTRL_05 (0x1986 << 2) |
| #define VPU_VPP2_DNLP_CTRL_06 (0x1987 << 2) |
| #define VPU_VPP2_DNLP_CTRL_07 (0x1988 << 2) |
| #define VPU_VPP2_DNLP_CTRL_08 (0x1989 << 2) |
| #define VPU_VPP2_DNLP_CTRL_09 (0x198a << 2) |
| #define VPU_VPP2_DNLP_CTRL_10 (0x198b << 2) |
| #define VPU_VPP2_DNLP_CTRL_11 (0x198c << 2) |
| #define VPU_VPP2_DNLP_CTRL_12 (0x198d << 2) |
| #define VPU_VPP2_DNLP_CTRL_13 (0x198e << 2) |
| #define VPU_VPP2_DNLP_CTRL_14 (0x198f << 2) |
| #define VPU_VPP2_DNLP_CTRL_15 (0x1990 << 2) |
| #define VPU_VPP2_VE_ENABLE_CTRL (0x19a1 << 2) |
| #define VPU_VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH (0x19a2 << 2) |
| #define VPU_VPP2_VE_DEMO_CENTER_BAR (0x19a3 << 2) |
| #define VPU_VPP2_VE_H_V_SIZE (0x19a4 << 2) |
| #define VPU_VPP2_VDO_MEAS_CTRL (0x19a8 << 2) |
| #define VPU_VPP2_VDO_MEAS_VS_COUNT_HI (0x19a9 << 2) |
| #define VPU_VPP2_VDO_MEAS_VS_COUNT_LO (0x19aa << 2) |
| #define VPU_VPP2_OSD_VSC_PHASE_STEP (0x19c0 << 2) |
| #define VPU_VPP2_OSD_VSC_INI_PHASE (0x19c1 << 2) |
| #define VPU_VPP2_OSD_VSC_CTRL0 (0x19c2 << 2) |
| #define VPU_VPP2_OSD_HSC_PHASE_STEP (0x19c3 << 2) |
| #define VPU_VPP2_OSD_HSC_INI_PHASE (0x19c4 << 2) |
| #define VPU_VPP2_OSD_HSC_CTRL0 (0x19c5 << 2) |
| #define VPU_VPP2_OSD_HSC_INI_PAT_CTRL (0x19c6 << 2) |
| #define VPU_VPP2_OSD_SC_DUMMY_DATA (0x19c7 << 2) |
| #define VPU_VPP2_OSD_SC_CTRL0 (0x19c8 << 2) |
| #define VPU_VPP2_OSD_SCI_WH_M1 (0x19c9 << 2) |
| #define VPU_VPP2_OSD_SCO_H_START_END (0x19ca << 2) |
| #define VPU_VPP2_OSD_SCO_V_START_END (0x19cb << 2) |
| #define VPU_VPP2_OSD_SCALE_COEF_IDX (0x19cc << 2) |
| #define VPU_VPP2_OSD_SCALE_COEF (0x19cd << 2) |
| #define VPU_VPP2_INT_LINE_NUM (0x19ce << 2) |
| #define VPU_VPP_DUMMY_DATA (0x1d00 << 2) |
| #define VPU_VPP_LINE_IN_LENGTH (0x1d01 << 2) |
| #define VPU_VPP_PIC_IN_HEIGHT (0x1d02 << 2) |
| #define VPU_VPP_SCALE_COEF_IDX (0x1d03 << 2) |
| #define VPU_VPP_SCALE_COEF (0x1d04 << 2) |
| #define VPU_VPP_VSC_REGION12_STARTP (0x1d05 << 2) |
| #define VPU_VPP_VSC_REGION34_STARTP (0x1d06 << 2) |
| #define VPU_VPP_VSC_REGION4_ENDP (0x1d07 << 2) |
| #define VPU_VPP_VSC_START_PHASE_STEP (0x1d08 << 2) |
| #define VPU_VPP_VSC_REGION0_PHASE_SLOPE (0x1d09 << 2) |
| #define VPU_VPP_VSC_REGION1_PHASE_SLOPE (0x1d0a << 2) |
| #define VPU_VPP_VSC_REGION3_PHASE_SLOPE (0x1d0b << 2) |
| #define VPU_VPP_VSC_REGION4_PHASE_SLOPE (0x1d0c << 2) |
| #define VPU_VPP_VSC_PHASE_CTRL (0x1d0d << 2) |
| #define VPU_VPP_VSC_INI_PHASE (0x1d0e << 2) |
| #define VPU_VPP_HSC_REGION12_STARTP (0x1d10 << 2) |
| #define VPU_VPP_HSC_REGION34_STARTP (0x1d11 << 2) |
| #define VPU_VPP_HSC_REGION4_ENDP (0x1d12 << 2) |
| #define VPU_VPP_HSC_START_PHASE_STEP (0x1d13 << 2) |
| #define VPU_VPP_HSC_REGION0_PHASE_SLOPE (0x1d14 << 2) |
| #define VPU_VPP_HSC_REGION1_PHASE_SLOPE (0x1d15 << 2) |
| #define VPU_VPP_HSC_REGION3_PHASE_SLOPE (0x1d16 << 2) |
| #define VPU_VPP_HSC_REGION4_PHASE_SLOPE (0x1d17 << 2) |
| #define VPU_VPP_HSC_PHASE_CTRL (0x1d18 << 2) |
| #define VPU_VPP_SC_MISC (0x1d19 << 2) |
| #define VPU_VPP_PREBLEND_VD1_H_START_END (0x1d1a << 2) |
| #define VPU_VPP_PREBLEND_VD1_V_START_END (0x1d1b << 2) |
| #define VPU_VPP_POSTBLEND_VD1_H_START_END (0x1d1c << 2) |
| #define VPU_VPP_POSTBLEND_VD1_V_START_END (0x1d1d << 2) |
| #define VPU_VPP_BLEND_VD2_H_START_END (0x1d1e << 2) |
| #define VPU_VPP_BLEND_VD2_V_START_END (0x1d1f << 2) |
| #define VPU_VPP_PREBLEND_H_SIZE (0x1d20 << 2) |
| #define VPU_VPP_POSTBLEND_H_SIZE (0x1d21 << 2) |
| #define VPU_VPP_HOLD_LINES (0x1d22 << 2) |
| #define VPU_VPP_BLEND_ONECOLOR_CTRL (0x1d23 << 2) |
| #define VPU_VPP_PREBLEND_CURRENT_XY (0x1d24 << 2) |
| #define VPU_VPP_POSTBLEND_CURRENT_XY (0x1d25 << 2) |
| #define VPU_VPP_MISC (0x1d26 << 2) |
| #define VPU_VPP_OFIFO_SIZE (0x1d27 << 2) |
| #define VPU_VPP_FIFO_STATUS (0x1d28 << 2) |
| #define VPU_VPP_SMOKE_CTRL (0x1d29 << 2) |
| #define VPU_VPP_SMOKE1_VAL (0x1d2a << 2) |
| #define VPU_VPP_SMOKE2_VAL (0x1d2b << 2) |
| #define VPU_VPP_SMOKE3_VAL (0x1d2c << 2) |
| #define VPU_VPP_SMOKE1_H_START_END (0x1d2d << 2) |
| #define VPU_VPP_SMOKE1_V_START_END (0x1d2e << 2) |
| #define VPU_VPP_SMOKE2_H_START_END (0x1d2f << 2) |
| #define VPU_VPP_SMOKE2_V_START_END (0x1d30 << 2) |
| #define VPU_VPP_SMOKE3_H_START_END (0x1d31 << 2) |
| #define VPU_VPP_SMOKE3_V_START_END (0x1d32 << 2) |
| #define VPU_VPP_SCO_FIFO_CTRL (0x1d33 << 2) |
| #define VPU_VPP_HSC_PHASE_CTRL1 (0x1d34 << 2) |
| #define VPU_VPP_HSC_INI_PAT_CTRL (0x1d35 << 2) |
| #define VPU_VPP_VADJ_CTRL (0x1d40 << 2) |
| #define VPU_VPP_VADJ1_Y (0x1d41 << 2) |
| #define VPU_VPP_VADJ1_MA_MB (0x1d42 << 2) |
| #define VPU_VPP_VADJ1_MC_MD (0x1d43 << 2) |
| #define VPU_VPP_VADJ2_Y (0x1d44 << 2) |
| #define VPU_VPP_VADJ2_MA_MB (0x1d45 << 2) |
| #define VPU_VPP_VADJ2_MC_MD (0x1d46 << 2) |
| #define VPU_VPP_HSHARP_CTRL (0x1d50 << 2) |
| #define VPU_VPP_HSHARP_LUMA_THRESH01 (0x1d51 << 2) |
| #define VPU_VPP_HSHARP_LUMA_THRESH23 (0x1d52 << 2) |
| #define VPU_VPP_HSHARP_CHROMA_THRESH01 (0x1d53 << 2) |
| #define VPU_VPP_HSHARP_CHROMA_THRESH23 (0x1d54 << 2) |
| #define VPU_VPP_HSHARP_LUMA_GAIN (0x1d55 << 2) |
| #define VPU_VPP_HSHARP_CHROMA_GAIN (0x1d56 << 2) |
| #define VPU_VPP_MATRIX_PROBE_COLOR (0x1d5c << 2) |
| #define VPU_VPP_MATRIX_PROBE_COLOR1 (0x1dd7 << 2) |
| #define VPU_VPP_MATRIX_HL_COLOR (0x1d5d << 2) |
| #define VPU_VPP_MATRIX_PROBE_POS (0x1d5e << 2) |
| #define VPU_VPP_MATRIX_CTRL (0x1d5f << 2) |
| #define VPU_VPP_MATRIX_COEF00_01 (0x1d60 << 2) |
| #define VPU_VPP_MATRIX_COEF02_10 (0x1d61 << 2) |
| #define VPU_VPP_MATRIX_COEF11_12 (0x1d62 << 2) |
| #define VPU_VPP_MATRIX_COEF20_21 (0x1d63 << 2) |
| #define VPU_VPP_MATRIX_COEF22 (0x1d64 << 2) |
| #define VPU_VPP_MATRIX_OFFSET0_1 (0x1d65 << 2) |
| #define VPU_VPP_MATRIX_OFFSET2 (0x1d66 << 2) |
| #define VPU_VPP_MATRIX_PRE_OFFSET0_1 (0x1d67 << 2) |
| #define VPU_VPP_MATRIX_PRE_OFFSET2 (0x1d68 << 2) |
| #define VPU_VPP_DUMMY_DATA1 (0x1d69 << 2) |
| #define VPU_VPP_GAINOFF_CTRL0 (0x1d6a << 2) |
| #define VPU_VPP_GAINOFF_CTRL1 (0x1d6b << 2) |
| #define VPU_VPP_GAINOFF_CTRL2 (0x1d6c << 2) |
| #define VPU_VPP_GAINOFF_CTRL3 (0x1d6d << 2) |
| #define VPU_VPP_GAINOFF_CTRL4 (0x1d6e << 2) |
| #define VPU_VPP_CHROMA_ADDR_PORT (0x1d70 << 2) |
| #define VPU_VPP_CHROMA_DATA_PORT (0x1d71 << 2) |
| #define VPU_VPP_GCLK_CTRL0 (0x1d72 << 2) |
| #define VPU_VPP_GCLK_CTRL1 (0x1d73 << 2) |
| #define VPU_VPP_SC_GCLK_CTRL (0x1d74 << 2) |
| #define VPU_VPP_MISC1 (0x1d76 << 2) |
| #define VPU_VPP_SRSCL_GCLK_CTRL (0x1d77 << 2) |
| #define VPU_VPP_OSDSR_GCLK_CTRL (0x1d78 << 2) |
| #define VPU_VPP_XVYCC_GCLK_CTRL (0x1d79 << 2) |
| #define VPU_VPP_BLACKEXT_CTRL (0x1d80 << 2) |
| #define VPU_VPP_DNLP_CTRL_00 (0x1d81 << 2) |
| #define VPU_VPP_DNLP_CTRL_01 (0x1d82 << 2) |
| #define VPU_VPP_DNLP_CTRL_02 (0x1d83 << 2) |
| #define VPU_VPP_DNLP_CTRL_03 (0x1d84 << 2) |
| #define VPU_VPP_DNLP_CTRL_04 (0x1d85 << 2) |
| #define VPU_VPP_DNLP_CTRL_05 (0x1d86 << 2) |
| #define VPU_VPP_DNLP_CTRL_06 (0x1d87 << 2) |
| #define VPU_VPP_DNLP_CTRL_07 (0x1d88 << 2) |
| #define VPU_VPP_DNLP_CTRL_08 (0x1d89 << 2) |
| #define VPU_VPP_DNLP_CTRL_09 (0x1d8a << 2) |
| #define VPU_VPP_DNLP_CTRL_10 (0x1d8b << 2) |
| #define VPU_VPP_DNLP_CTRL_11 (0x1d8c << 2) |
| #define VPU_VPP_DNLP_CTRL_12 (0x1d8d << 2) |
| #define VPU_VPP_DNLP_CTRL_13 (0x1d8e << 2) |
| #define VPU_VPP_DNLP_CTRL_14 (0x1d8f << 2) |
| #define VPU_VPP_DNLP_CTRL_15 (0x1d90 << 2) |
| #define VPU_VPP_SRSHARP0_CTRL (0x1d91 << 2) |
| #define VPU_VPP_SRSHARP1_CTRL (0x1d92 << 2) |
| #define VPU_VPP_DOLBY_CTRL (0x1d93 << 2) |
| #define VPU_VPP_DAT_CONV_PARA0 (0x1d94 << 2) |
| #define VPU_VPP_DAT_CONV_PARA1 (0x1d95 << 2) |
| #define VPU_VPP_SYNC_SEL0 (0x1d96 << 2) |
| #define VPU_VPP_VADJ1_BLACK_VAL (0x1d97 << 2) |
| #define VPU_VPP_VADJ2_BLACK_VAL (0x1d98 << 2) |
| #define VPU_VPP_BLUE_STRETCH_1 (0x1d9c << 2) |
| #define VPU_VPP_BLUE_STRETCH_2 (0x1d9d << 2) |
| #define VPU_VPP_BLUE_STRETCH_3 (0x1d9e << 2) |
| #define VPU_VPP_CCORING_CTRL (0x1da0 << 2) |
| #define VPU_VPP_VE_ENABLE_CTRL (0x1da1 << 2) |
| #define VPU_VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH (0x1da2 << 2) |
| #define VPU_VPP_VE_DEMO_CENTER_BAR (0x1da3 << 2) |
| #define VPU_VPP_VE_H_V_SIZE (0x1da4 << 2) |
| #define VPU_VPP_OUT_H_V_SIZE (0x1da5 << 2) |
| #define VPU_VPP_IN_H_V_SIZE (0x1da6 << 2) |
| #define VPU_VPP_VDO_MEAS_CTRL (0x1da8 << 2) |
| #define VPU_VPP_VDO_MEAS_VS_COUNT_HI (0x1da9 << 2) |
| #define VPU_VPP_VDO_MEAS_VS_COUNT_LO (0x1daa << 2) |
| #define VPU_VPP_INPUT_CTRL (0x1dab << 2) |
| #define VPU_VPP_CTI_CTRL2 (0x1dac << 2) |
| #define VPU_VPP_PEAKING_SAT_THD1 (0x1dad << 2) |
| #define VPU_VPP_PEAKING_SAT_THD2 (0x1dae << 2) |
| #define VPU_VPP_PEAKING_SAT_THD3 (0x1daf << 2) |
| #define VPU_VPP_PEAKING_SAT_THD4 (0x1db0 << 2) |
| #define VPU_VPP_PEAKING_SAT_THD5 (0x1db1 << 2) |
| #define VPU_VPP_PEAKING_SAT_THD6 (0x1db2 << 2) |
| #define VPU_VPP_PEAKING_SAT_THD7 (0x1db3 << 2) |
| #define VPU_VPP_PEAKING_SAT_THD8 (0x1db4 << 2) |
| #define VPU_VPP_PEAKING_SAT_THD9 (0x1db5 << 2) |
| #define VPU_VPP_PEAKING_GAIN_ADD1 (0x1db6 << 2) |
| #define VPU_VPP_PEAKING_GAIN_ADD2 (0x1db7 << 2) |
| #define VPU_VPP_PEAKING_DNLP (0x1db8 << 2) |
| #define VPU_VPP_SHARP_DEMO_WIN_CTRL1 (0x1db9 << 2) |
| #define VPU_VPP_SHARP_DEMO_WIN_CTRL2 (0x1dba << 2) |
| #define VPU_VPP_FRONT_HLTI_CTRL (0x1dbb << 2) |
| #define VPU_VPP_FRONT_CTI_CTRL (0x1dbc << 2) |
| #define VPU_VPP_FRONT_CTI_CTRL2 (0x1dbd << 2) |
| #define VPU_VPP_OSD_VSC_PHASE_STEP (0x1dc0 << 2) |
| #define VPU_VPP_OSD_VSC_INI_PHASE (0x1dc1 << 2) |
| #define VPU_VPP_OSD_VSC_CTRL0 (0x1dc2 << 2) |
| #define VPU_VPP_OSD_HSC_PHASE_STEP (0x1dc3 << 2) |
| #define VPU_VPP_OSD_HSC_INI_PHASE (0x1dc4 << 2) |
| #define VPU_VPP_OSD_HSC_CTRL0 (0x1dc5 << 2) |
| #define VPU_VPP_OSD_HSC_INI_PAT_CTRL (0x1dc6 << 2) |
| #define VPU_VPP_OSD_SC_DUMMY_DATA (0x1dc7 << 2) |
| #define VPU_VPP_OSD_SC_CTRL0 (0x1dc8 << 2) |
| #define VPU_VPP_OSD_SCI_WH_M1 (0x1dc9 << 2) |
| #define VPU_VPP_OSD_SCO_H_START_END (0x1dca << 2) |
| #define VPU_VPP_OSD_SCO_V_START_END (0x1dcb << 2) |
| #define VPU_VPP_OSD_SCALE_COEF_IDX (0x1dcc << 2) |
| #define VPU_VPP_OSD_SCALE_COEF (0x1dcd << 2) |
| #define VPU_VPP_INT_LINE_NUM (0x1dce << 2) |
| #define VPU_VPP_XVYCC_MISC (0x1dcf << 2) |
| #define VPU_VPP_HLTI_DN_FLT (0x1dd0 << 2) |
| #define VPU_VPP_HLTI_GAIN (0x1dd1 << 2) |
| #define VPU_VPP_HLTI_PARA (0x1dd2 << 2) |
| #define VPU_VPP_HCTI_DN_FLT (0x1dd3 << 2) |
| #define VPU_VPP_HCTI_GAIN (0x1dd4 << 2) |
| #define VPU_VPP_HCTI_PARA (0x1dd5 << 2) |
| #define VPU_VPP_VCTI_PARA (0x1dd6 << 2) |
| #define VPU_VPP_OFIFO_URG_CTRL (0x1dd8 << 2) |
| #define VPU_VPP_CLIP_MISC0 (0x1dd9 << 2) |
| #define VPU_VPP_CLIP_MISC1 (0x1dda << 2) |
| #define VPU_VPP_MATRIX_COEF13_14 (0x1ddb << 2) |
| #define VPU_VPP_MATRIX_COEF23_24 (0x1ddc << 2) |
| #define VPU_VPP_MATRIX_COEF15_25 (0x1ddd << 2) |
| #define VPU_VPP_MATRIX_CLIP (0x1dde << 2) |
| #define VPU_VPP_XVYCC_MISC0 (0x1ddf << 2) |
| #define VPU_VPP_XVYCC_MISC1 (0x1de0 << 2) |
| #define VPU_VPP_VD1_CLIP_MISC0 (0x1de1 << 2) |
| #define VPU_VPP_VD1_CLIP_MISC1 (0x1de2 << 2) |
| #define VPU_VPP_VD2_CLIP_MISC0 (0x1de3 << 2) |
| #define VPU_VPP_VD2_CLIP_MISC1 (0x1de4 << 2) |
| #define VPU_VPP_VE_DITHER_CTRL (0x3120 << 2) |
| #define VPU_VPP_VE_DITHER_LUT_1 (0x3121 << 2) |
| #define VPU_VPP_VE_DITHER_LUT_2 (0x3122 << 2) |
| #define VPU_VPP_VE_DITHER_LUT_3 (0x3123 << 2) |
| #define VPU_VPP_VE_DITHER_LUT_4 (0x3124 << 2) |
| #define VPU_VPP_VE_DITHER_LUT_5 (0x3125 << 2) |
| #define VPU_VPP_VE_DITHER_LUT_6 (0x3126 << 2) |
| #define VPU_VPP_VE_DITHER_LUT_7 (0x3127 << 2) |
| #define VPU_VPP_VE_DITHER_LUT_8 (0x3128 << 2) |
| #define VPU_VPP_VE_DITHER_LUT_9 (0x3129 << 2) |
| #define VPU_VPP_VE_DITHER_LUT_10 (0x312a << 2) |
| #define VPU_VPP_VE_DITHER_LUT_11 (0x312b << 2) |
| #define VPU_VPP_VE_DITHER_LUT_12 (0x312c << 2) |
| #define VPU_VPP_OSDSC_DITHER_CTRL (0x3130 << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_1 (0x3131 << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_2 (0x3132 << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_3 (0x3133 << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_4 (0x3134 << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_5 (0x3135 << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_6 (0x3136 << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_7 (0x3137 << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_8 (0x3138 << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_9 (0x3139 << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_10 (0x313a << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_11 (0x313b << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_12 (0x313c << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_13 (0x313d << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_14 (0x313e << 2) |
| #define VPU_VPP_OSDSC_DITHER_LUT_15 (0x313f << 2) |
| #define VPU_VPP_EOTF_CTL (0x31d0 << 2) |
| #define VPU_VPP_EOTF_COEF00_01 (0x31d1 << 2) |
| #define VPU_VPP_EOTF_COEF02_10 (0x31d2 << 2) |
| #define VPU_VPP_EOTF_COEF11_12 (0x31d3 << 2) |
| #define VPU_VPP_EOTF_COEF20_21 (0x31d4 << 2) |
| #define VPU_VPP_EOTF_COEF22_RS (0x31d5 << 2) |
| #define VPU_VPP_EOTF_LUT_ADDR_PORT (0x31d6 << 2) |
| #define VPU_VPP_EOTF_LUT_DATA_PORT (0x31d7 << 2) |
| #define VPU_VPP_EOTF_3X3_OFST_0 (0x31d8 << 2) |
| #define VPU_VPP_EOTF_3X3_OFST_1 (0x31d9 << 2) |
| #define VPU_VPP_VD2_HDR_IN_SIZE (0x1df0 << 2) |
| #define VPU_VPP_OSD1_IN_SIZE (0x1df1 << 2) |
| #define VPU_VPP_GCLK_CTRL2 (0x1df2 << 2) |
| #define VPU_VPP_OSD1_BLD_H_SCOPE (0x1df5 << 2) |
| #define VPU_VPP_OSD1_BLD_V_SCOPE (0x1df6 << 2) |
| #define VPU_VPP_OSD2_BLD_H_SCOPE (0x1df7 << 2) |
| #define VPU_VPP_OSD2_BLD_V_SCOPE (0x1df8 << 2) |
| #define VPU_VPP_WRBAK_CTRL (0x1df9 << 2) |
| #define VPU_VPP_SLEEP_CTRL (0x1dfa << 2) |
| #define VPU_VPP_POST_BLEND_BLEND_DUMMY_DATA (0x3968 << 2) |
| #define VPU_VPP_POST_BLEND_DUMMY_ALPHA (0x3969 << 2) |
| #define VPU_VPP_POST2_MATRIX_COEF00_01 (0x39a0 << 2) |
| #define VPU_VPP_POST2_MATRIX_COEF02_10 (0x39a1 << 2) |
| #define VPU_VPP_POST2_MATRIX_COEF11_12 (0x39a2 << 2) |
| #define VPU_VPP_POST2_MATRIX_COEF20_21 (0x39a3 << 2) |
| #define VPU_VPP_POST2_MATRIX_COEF22 (0x39a4 << 2) |
| #define VPU_VPP_POST2_MATRIX_COEF13_14 (0x39a5 << 2) |
| #define VPU_VPP_POST2_MATRIX_COEF23_24 (0x39a6 << 2) |
| #define VPU_VPP_POST2_MATRIX_COEF15_25 (0x39a7 << 2) |
| #define VPU_VPP_POST2_MATRIX_CLIP (0x39a8 << 2) |
| #define VPU_VPP_POST2_MATRIX_OFFSET0_1 (0x39a9 << 2) |
| #define VPU_VPP_POST2_MATRIX_OFFSET2 (0x39aa << 2) |
| #define VPU_VPP_POST2_MATRIX_PRE_OFFSET0_1 (0x39ab << 2) |
| #define VPU_VPP_POST2_MATRIX_PRE_OFFSET2 (0x39ac << 2) |
| #define VPU_VPP_POST2_MATRIX_EN_CTRL (0x39ad << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_COEF00_01 (0x3d60 << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_COEF02_10 (0x3d61 << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_COEF11_12 (0x3d62 << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_COEF20_21 (0x3d63 << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_COEF22 (0x3d64 << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_COEF13_14 (0x3d65 << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_COEF23_24 (0x3d66 << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_COEF15_25 (0x3d67 << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_CLIP (0x3d68 << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_OFFSET0_1 (0x3d69 << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_OFFSET2 (0x3d6a << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 (0x3d6b << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 (0x3d6c << 2) |
| #define VPU_VPP_WRAP_OSD1_MATRIX_EN_CTRL (0x3d6d << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_COEF00_01 (0x3d70 << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_COEF02_10 (0x3d71 << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_COEF11_12 (0x3d72 << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_COEF20_21 (0x3d73 << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_COEF22 (0x3d74 << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_COEF13_14 (0x3d75 << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_COEF23_24 (0x3d76 << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_COEF15_25 (0x3d77 << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_CLIP (0x3d78 << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_OFFSET0_1 (0x3d79 << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_OFFSET2 (0x3d7a << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 (0x3d7b << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 (0x3d7c << 2) |
| #define VPU_VPP_WRAP_OSD2_MATRIX_EN_CTRL (0x3d7d << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_COEF00_01 (0x3db0 << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_COEF02_10 (0x3db1 << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_COEF11_12 (0x3db2 << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_COEF20_21 (0x3db3 << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_COEF22 (0x3db4 << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_COEF13_14 (0x3db5 << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_COEF23_24 (0x3db6 << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_COEF15_25 (0x3db7 << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_CLIP (0x3db8 << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_OFFSET0_1 (0x3db9 << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_OFFSET2 (0x3dba << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 (0x3dbb << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 (0x3dbc << 2) |
| #define VPU_VPP_WRAP_OSD3_MATRIX_EN_CTRL (0x3dbd << 2) |
| |
| #define VPU_ENCP_VFIFO2VD_CTL (0x1b58 << 2) |
| #define VPU_ENCP_VFIFO2VD_PIXEL_START (0x1b59 << 2) |
| #define VPU_ENCP_VFIFO2VD_PIXEL_END (0x1b5a << 2) |
| #define VPU_ENCP_VFIFO2VD_LINE_TOP_START (0x1b5b << 2) |
| #define VPU_ENCP_VFIFO2VD_LINE_TOP_END (0x1b5c << 2) |
| #define VPU_ENCP_VFIFO2VD_LINE_BOT_START (0x1b5d << 2) |
| #define VPU_ENCP_VFIFO2VD_LINE_BOT_END (0x1b5e << 2) |
| #define VPU_ENCL_TCON_INVERT_CTL (0x1bfd << 2) |
| #define VPU_ENCP_VIDEO_EN (0x1b80 << 2) |
| #define VPU_ENCP_VIDEO_SYNC_MODE (0x1b81 << 2) |
| #define VPU_ENCP_MACV_EN (0x1b82 << 2) |
| #define VPU_ENCP_VIDEO_Y_SCL (0x1b83 << 2) |
| #define VPU_ENCP_VIDEO_PB_SCL (0x1b84 << 2) |
| #define VPU_ENCP_VIDEO_PR_SCL (0x1b85 << 2) |
| #define VPU_ENCP_VIDEO_SYNC_SCL (0x1b86 << 2) |
| #define VPU_ENCP_VIDEO_MACV_SCL (0x1b87 << 2) |
| #define VPU_ENCP_VIDEO_Y_OFFST (0x1b88 << 2) |
| #define VPU_ENCP_VIDEO_PB_OFFST (0x1b89 << 2) |
| #define VPU_ENCP_VIDEO_PR_OFFST (0x1b8a << 2) |
| #define VPU_ENCP_VIDEO_SYNC_OFFST (0x1b8b << 2) |
| #define VPU_ENCP_VIDEO_MACV_OFFST (0x1b8c << 2) |
| #define VPU_ENCP_VIDEO_MODE (0x1b8d << 2) |
| #define VPU_ENCP_VIDEO_MODE_ADV (0x1b8e << 2) |
| #define VPU_ENCP_DBG_PX_RST (0x1b90 << 2) |
| #define VPU_ENCP_DBG_LN_RST (0x1b91 << 2) |
| #define VPU_ENCP_DBG_PX_INT (0x1b92 << 2) |
| #define VPU_ENCP_DBG_LN_INT (0x1b93 << 2) |
| #define VPU_ENCP_VIDEO_YFP1_HTIME (0x1b94 << 2) |
| #define VPU_ENCP_VIDEO_YFP2_HTIME (0x1b95 << 2) |
| #define VPU_ENCP_VIDEO_YC_DLY (0x1b96 << 2) |
| #define VPU_ENCP_VIDEO_MAX_PXCNT (0x1b97 << 2) |
| #define VPU_ENCP_VIDEO_HSPULS_BEGIN (0x1b98 << 2) |
| #define VPU_ENCP_VIDEO_HSPULS_END (0x1b99 << 2) |
| #define VPU_ENCP_VIDEO_HSPULS_SWITCH (0x1b9a << 2) |
| #define VPU_ENCP_VIDEO_VSPULS_BEGIN (0x1b9b << 2) |
| #define VPU_ENCP_VIDEO_VSPULS_END (0x1b9c << 2) |
| #define VPU_ENCP_VIDEO_VSPULS_BLINE (0x1b9d << 2) |
| #define VPU_ENCP_VIDEO_VSPULS_ELINE (0x1b9e << 2) |
| #define VPU_ENCP_VIDEO_EQPULS_BEGIN (0x1b9f << 2) |
| #define VPU_ENCP_VIDEO_EQPULS_END (0x1ba0 << 2) |
| #define VPU_ENCP_VIDEO_EQPULS_BLINE (0x1ba1 << 2) |
| #define VPU_ENCP_VIDEO_EQPULS_ELINE (0x1ba2 << 2) |
| #define VPU_ENCP_VIDEO_HAVON_END (0x1ba3 << 2) |
| #define VPU_ENCP_VIDEO_HAVON_BEGIN (0x1ba4 << 2) |
| #define VPU_ENCP_VIDEO_VAVON_ELINE (0x1baf << 2) |
| #define VPU_ENCP_VIDEO_VAVON_BLINE (0x1ba6 << 2) |
| #define VPU_ENCP_VIDEO_HSO_BEGIN (0x1ba7 << 2) |
| #define VPU_ENCP_VIDEO_HSO_END (0x1ba8 << 2) |
| #define VPU_ENCP_VIDEO_VSO_BEGIN (0x1ba9 << 2) |
| #define VPU_ENCP_VIDEO_VSO_END (0x1baa << 2) |
| #define VPU_ENCP_VIDEO_VSO_BLINE (0x1bab << 2) |
| #define VPU_ENCP_VIDEO_VSO_ELINE (0x1bac << 2) |
| #define VPU_ENCP_VIDEO_SYNC_WAVE_CURVE (0x1bad << 2) |
| #define VPU_ENCP_VIDEO_MAX_LNCNT (0x1bae << 2) |
| #define VPU_ENCP_VIDEO_SY_VAL (0x1bb0 << 2) |
| #define VPU_ENCP_VIDEO_SY2_VAL (0x1bb1 << 2) |
| #define VPU_ENCP_VIDEO_BLANKY_VAL (0x1bb2 << 2) |
| #define VPU_ENCP_VIDEO_BLANKPB_VAL (0x1bb3 << 2) |
| #define VPU_ENCP_VIDEO_BLANKPR_VAL (0x1bb4 << 2) |
| #define VPU_ENCP_VIDEO_HOFFST (0x1bb5 << 2) |
| #define VPU_ENCP_VIDEO_VOFFST (0x1bb6 << 2) |
| #define VPU_ENCP_VIDEO_RGB_CTRL (0x1bb7 << 2) |
| #define VPU_ENCP_VIDEO_FILT_CTRL (0x1bb8 << 2) |
| #define VPU_ENCP_VIDEO_OFLD_VPEQ_OFST (0x1bb9 << 2) |
| #define VPU_ENCP_VIDEO_OFLD_VOAV_OFST (0x1bba << 2) |
| #define VPU_ENCP_VIDEO_MATRIX_CB (0x1bbb << 2) |
| #define VPU_ENCP_VIDEO_MATRIX_CR (0x1bbc << 2) |
| #define VPU_ENCP_VIDEO_RGBIN_CTRL (0x1bbd << 2) |
| #define VPU_ENCP_MACV_BLANKY_VAL (0x1bc0 << 2) |
| #define VPU_ENCP_MACV_MAXY_VAL (0x1bc1 << 2) |
| #define VPU_ENCP_MACV_1ST_PSSYNC_STRT (0x1bc2 << 2) |
| #define VPU_ENCP_MACV_PSSYNC_STRT (0x1bc3 << 2) |
| #define VPU_ENCP_MACV_AGC_STRT (0x1bc4 << 2) |
| #define VPU_ENCP_MACV_AGC_END (0x1bc5 << 2) |
| #define VPU_ENCP_MACV_WAVE_END (0x1bc6 << 2) |
| #define VPU_ENCP_MACV_STRTLINE (0x1bc7 << 2) |
| #define VPU_ENCP_MACV_ENDLINE (0x1bc8 << 2) |
| #define VPU_ENCP_MACV_TS_CNT_MAX_L (0x1bc9 << 2) |
| #define VPU_ENCP_MACV_TS_CNT_MAX_H (0x1bca << 2) |
| #define VPU_ENCP_MACV_TIME_DOWN (0x1bcb << 2) |
| #define VPU_ENCP_MACV_TIME_LO (0x1bcc << 2) |
| #define VPU_ENCP_MACV_TIME_UP (0x1bcd << 2) |
| #define VPU_ENCP_MACV_TIME_RST (0x1bce << 2) |
| #define VPU_ENCP_VBI_CTRL (0x1bd0 << 2) |
| #define VPU_ENCP_VBI_SETTING (0x1bd1 << 2) |
| #define VPU_ENCP_VBI_BEGIN (0x1bd2 << 2) |
| #define VPU_ENCP_VBI_WIDTH (0x1bd3 << 2) |
| #define VPU_ENCP_VBI_HVAL (0x1bd4 << 2) |
| #define VPU_ENCP_VBI_DATA0 (0x1bd5 << 2) |
| #define VPU_ENCP_VBI_DATA1 (0x1bd6 << 2) |
| #define VPU_ENCI_VIDEO_MODE (0x1b00 << 2) |
| #define VPU_ENCI_VIDEO_MODE_ADV (0x1b01 << 2) |
| #define VPU_ENCI_VIDEO_FSC_ADJ (0x1b02 << 2) |
| #define VPU_ENCI_VIDEO_BRIGHT (0x1b03 << 2) |
| #define VPU_ENCI_VIDEO_CONT (0x1b04 << 2) |
| #define VPU_ENCI_VIDEO_SAT (0x1b05 << 2) |
| #define VPU_ENCI_VIDEO_HUE (0x1b06 << 2) |
| #define VPU_ENCI_VIDEO_SCH (0x1b07 << 2) |
| #define VPU_ENCI_SYNC_MODE (0x1b08 << 2) |
| #define VPU_ENCI_SYNC_CTRL (0x1b09 << 2) |
| #define VPU_ENCI_SYNC_HSO_BEGIN (0x1b0a << 2) |
| #define VPU_ENCI_SYNC_HSO_END (0x1b0b << 2) |
| #define VPU_ENCI_SYNC_VSO_EVN (0x1b0c << 2) |
| #define VPU_ENCI_SYNC_VSO_ODD (0x1b0d << 2) |
| #define VPU_ENCI_SYNC_VSO_EVNLN (0x1b0e << 2) |
| #define VPU_ENCI_SYNC_VSO_ODDLN (0x1b0f << 2) |
| #define VPU_ENCI_SYNC_HOFFST (0x1b10 << 2) |
| #define VPU_ENCI_SYNC_VOFFST (0x1b11 << 2) |
| #define VPU_ENCI_SYNC_ADJ (0x1b12 << 2) |
| #define VPU_ENCI_RGB_SETTING (0x1b13 << 2) |
| #define VPU_ENCI_DE_H_BEGIN (0x1b16 << 2) |
| #define VPU_ENCI_DE_H_END (0x1b17 << 2) |
| #define VPU_ENCI_DE_V_BEGIN_EVEN (0x1b18 << 2) |
| #define VPU_ENCI_DE_V_END_EVEN (0x1b19 << 2) |
| #define VPU_ENCI_DE_V_BEGIN_ODD (0x1b1a << 2) |
| #define VPU_ENCI_DE_V_END_ODD (0x1b1b << 2) |
| #define VPU_ENCI_VBI_SETTING (0x1b20 << 2) |
| #define VPU_ENCI_VBI_CCDT_EVN (0x1b21 << 2) |
| #define VPU_ENCI_VBI_CCDT_ODD (0x1b22 << 2) |
| #define VPU_ENCI_VBI_CC525_LN (0x1b23 << 2) |
| #define VPU_ENCI_VBI_CC625_LN (0x1b24 << 2) |
| #define VPU_ENCI_VBI_WSSDT (0x1b25 << 2) |
| #define VPU_ENCI_VBI_WSS_LN (0x1b26 << 2) |
| #define VPU_ENCI_VBI_CGMSDT_L (0x1b27 << 2) |
| #define VPU_ENCI_VBI_CGMSDT_H (0x1b28 << 2) |
| #define VPU_ENCI_VBI_CGMS_LN (0x1b29 << 2) |
| #define VPU_ENCI_VBI_TTX_HTIME (0x1b2a << 2) |
| #define VPU_ENCI_VBI_TTX_LN (0x1b2b << 2) |
| #define VPU_ENCI_VBI_TTXDT0 (0x1b2c << 2) |
| #define VPU_ENCI_VBI_TTXDT1 (0x1b2d << 2) |
| #define VPU_ENCI_VBI_TTXDT2 (0x1b2e << 2) |
| #define VPU_ENCI_VBI_TTXDT3 (0x1b2f << 2) |
| #define VPU_ENCI_MACV_N0 (0x1b30 << 2) |
| #define VPU_ENCI_MACV_N1 (0x1b31 << 2) |
| #define VPU_ENCI_MACV_N2 (0x1b32 << 2) |
| #define VPU_ENCI_MACV_N3 (0x1b33 << 2) |
| #define VPU_ENCI_MACV_N4 (0x1b34 << 2) |
| #define VPU_ENCI_MACV_N5 (0x1b35 << 2) |
| #define VPU_ENCI_MACV_N6 (0x1b36 << 2) |
| #define VPU_ENCI_MACV_N7 (0x1b37 << 2) |
| #define VPU_ENCI_MACV_N8 (0x1b38 << 2) |
| #define VPU_ENCI_MACV_N9 (0x1b39 << 2) |
| #define VPU_ENCI_MACV_N10 (0x1b3a << 2) |
| #define VPU_ENCI_MACV_N11 (0x1b3b << 2) |
| #define VPU_ENCI_MACV_N12 (0x1b3c << 2) |
| #define VPU_ENCI_MACV_N13 (0x1b3d << 2) |
| #define VPU_ENCI_MACV_N14 (0x1b3e << 2) |
| #define VPU_ENCI_MACV_N15 (0x1b3f << 2) |
| #define VPU_ENCI_MACV_N16 (0x1b40 << 2) |
| #define VPU_ENCI_MACV_N17 (0x1b41 << 2) |
| #define VPU_ENCI_MACV_N18 (0x1b42 << 2) |
| #define VPU_ENCI_MACV_N19 (0x1b43 << 2) |
| #define VPU_ENCI_MACV_N20 (0x1b44 << 2) |
| #define VPU_ENCI_MACV_N21 (0x1b45 << 2) |
| #define VPU_ENCI_MACV_N22 (0x1b46 << 2) |
| #define VPU_ENCI_DBG_PX_RST (0x1b48 << 2) |
| #define VPU_ENCI_DBG_FLDLN_RST (0x1b49 << 2) |
| #define VPU_ENCI_DBG_PX_INT (0x1b4a << 2) |
| #define VPU_ENCI_DBG_FLDLN_INT (0x1b4b << 2) |
| #define VPU_ENCI_DBG_MAXPX (0x1b4c << 2) |
| #define VPU_ENCI_DBG_MAXLN (0x1b4d << 2) |
| #define VPU_ENCI_MACV_MAX_AMP (0x1b50 << 2) |
| #define VPU_ENCI_MACV_PULSE_LO (0x1b51 << 2) |
| #define VPU_ENCI_MACV_PULSE_HI (0x1b52 << 2) |
| #define VPU_ENCI_MACV_BKP_MAX (0x1b53 << 2) |
| #define VPU_ENCI_CFILT_CTRL (0x1b54 << 2) |
| #define VPU_ENCI_CFILT7 (0x1b55 << 2) |
| #define VPU_ENCI_YC_DELAY (0x1b56 << 2) |
| #define VPU_ENCI_VIDEO_EN (0x1b57 << 2) |
| #define VPU_ENCI_DVI_HSO_BEGIN (0x1c00 << 2) |
| #define VPU_ENCI_DVI_HSO_END (0x1c01 << 2) |
| #define VPU_ENCI_DVI_VSO_BLINE_EVN (0x1c02 << 2) |
| #define VPU_ENCI_DVI_VSO_BLINE_ODD (0x1c03 << 2) |
| #define VPU_ENCI_DVI_VSO_ELINE_EVN (0x1c04 << 2) |
| #define VPU_ENCI_DVI_VSO_ELINE_ODD (0x1c05 << 2) |
| #define VPU_ENCI_DVI_VSO_BEGIN_EVN (0x1c06 << 2) |
| #define VPU_ENCI_DVI_VSO_BEGIN_ODD (0x1c07 << 2) |
| #define VPU_ENCI_DVI_VSO_END_EVN (0x1c08 << 2) |
| #define VPU_ENCI_DVI_VSO_END_ODD (0x1c09 << 2) |
| #define VPU_ENCI_CFILT_CTRL2 (0x1c0a << 2) |
| #define VPU_ENCI_DACSEL_0 (0x1c0b << 2) |
| #define VPU_ENCI_DACSEL_1 (0x1c0c << 2) |
| #define VPU_ENCP_DACSEL_0 (0x1c0d << 2) |
| #define VPU_ENCP_DACSEL_1 (0x1c0e << 2) |
| #define VPU_ENCP_MAX_LINE_SWITCH_POINT (0x1c0f << 2) |
| #define VPU_ENCI_TST_EN (0x1c10 << 2) |
| #define VPU_ENCI_TST_MDSEL (0x1c11 << 2) |
| #define VPU_ENCI_TST_Y (0x1c12 << 2) |
| #define VPU_ENCI_TST_CB (0x1c13 << 2) |
| #define VPU_ENCI_TST_CR (0x1c14 << 2) |
| #define VPU_ENCI_TST_CLRBAR_STRT (0x1c15 << 2) |
| #define VPU_ENCI_TST_CLRBAR_WIDTH (0x1c16 << 2) |
| #define VPU_ENCI_TST_VDCNT_STSET (0x1c17 << 2) |
| #define VPU_ENCI_VFIFO2VD_CTL (0x1c18 << 2) |
| #define VPU_ENCI_VFIFO2VD_PIXEL_START (0x1c19 << 2) |
| #define VPU_ENCI_VFIFO2VD_PIXEL_END (0x1c1a << 2) |
| #define VPU_ENCI_VFIFO2VD_LINE_TOP_START (0x1c1b << 2) |
| #define VPU_ENCI_VFIFO2VD_LINE_TOP_END (0x1c1c << 2) |
| #define VPU_ENCI_VFIFO2VD_LINE_BOT_START (0x1c1d << 2) |
| #define VPU_ENCI_VFIFO2VD_LINE_BOT_END (0x1c1e << 2) |
| #define VPU_ENCI_VFIFO2VD_CTL2 (0x1c1f << 2) |
| #define VPU_ENCT_VFIFO2VD_CTL (0x1c20 << 2) |
| #define VPU_ENCT_VFIFO2VD_PIXEL_START (0x1c21 << 2) |
| #define VPU_ENCT_VFIFO2VD_PIXEL_END (0x1c22 << 2) |
| #define VPU_ENCT_VFIFO2VD_LINE_TOP_START (0x1c23 << 2) |
| #define VPU_ENCT_VFIFO2VD_LINE_TOP_END (0x1c24 << 2) |
| #define VPU_ENCT_VFIFO2VD_LINE_BOT_START (0x1c25 << 2) |
| #define VPU_ENCT_VFIFO2VD_LINE_BOT_END (0x1c26 << 2) |
| #define VPU_ENCT_VFIFO2VD_CTL2 (0x1c27 << 2) |
| #define VPU_ENCT_TST_EN (0x1c28 << 2) |
| #define VPU_ENCT_TST_MDSEL (0x1c29 << 2) |
| #define VPU_ENCT_TST_Y (0x1c2a << 2) |
| #define VPU_ENCT_TST_CB (0x1c2b << 2) |
| #define VPU_ENCT_TST_CR (0x1c2c << 2) |
| #define VPU_ENCT_TST_CLRBAR_STRT (0x1c2d << 2) |
| #define VPU_ENCT_TST_CLRBAR_WIDTH (0x1c2e << 2) |
| #define VPU_ENCT_TST_VDCNT_STSET (0x1c2f << 2) |
| #define VPU_ENCP_DVI_HSO_BEGIN (0x1c30 << 2) |
| #define VPU_ENCP_DVI_HSO_END (0x1c31 << 2) |
| #define VPU_ENCP_DVI_VSO_BLINE_EVN (0x1c32 << 2) |
| #define VPU_ENCP_DVI_VSO_BLINE_ODD (0x1c33 << 2) |
| #define VPU_ENCP_DVI_VSO_ELINE_EVN (0x1c34 << 2) |
| #define VPU_ENCP_DVI_VSO_ELINE_ODD (0x1c35 << 2) |
| #define VPU_ENCP_DVI_VSO_BEGIN_EVN (0x1c36 << 2) |
| #define VPU_ENCP_DVI_VSO_BEGIN_ODD (0x1c37 << 2) |
| #define VPU_ENCP_DVI_VSO_END_EVN (0x1c38 << 2) |
| #define VPU_ENCP_DVI_VSO_END_ODD (0x1c39 << 2) |
| #define VPU_ENCP_DE_H_BEGIN (0x1c3a << 2) |
| #define VPU_ENCP_DE_H_END (0x1c3b << 2) |
| #define VPU_ENCP_DE_V_BEGIN_EVEN (0x1c3c << 2) |
| #define VPU_ENCP_DE_V_END_EVEN (0x1c3d << 2) |
| #define VPU_ENCP_DE_V_BEGIN_ODD (0x1c3e << 2) |
| #define VPU_ENCP_DE_V_END_ODD (0x1c3f << 2) |
| #define VPU_ENCI_SYNC_LINE_LENGTH (0x1c40 << 2) |
| #define VPU_ENCI_SYNC_PIXEL_EN (0x1c41 << 2) |
| #define VPU_ENCI_SYNC_TO_LINE_EN (0x1c42 << 2) |
| #define VPU_ENCI_SYNC_TO_PIXEL (0x1c43 << 2) |
| #define VPU_ENCP_SYNC_LINE_LENGTH (0x1c44 << 2) |
| #define VPU_ENCP_SYNC_PIXEL_EN (0x1c45 << 2) |
| #define VPU_ENCP_SYNC_TO_LINE_EN (0x1c46 << 2) |
| #define VPU_ENCP_SYNC_TO_PIXEL (0x1c47 << 2) |
| #define VPU_ENCT_SYNC_LINE_LENGTH (0x1c48 << 2) |
| #define VPU_ENCT_SYNC_PIXEL_EN (0x1c49 << 2) |
| #define VPU_ENCT_SYNC_TO_LINE_EN (0x1c4a << 2) |
| #define VPU_ENCT_SYNC_TO_PIXEL (0x1c4b << 2) |
| #define VPU_ENCL_SYNC_LINE_LENGTH (0x1c4c << 2) |
| #define VPU_ENCL_SYNC_PIXEL_EN (0x1c4d << 2) |
| #define VPU_ENCL_SYNC_TO_LINE_EN (0x1c4e << 2) |
| #define VPU_ENCL_SYNC_TO_PIXEL (0x1c4f << 2) |
| #define VPU_ENCP_VFIFO2VD_CTL2 (0x1c50 << 2) |
| #define VPU_ENCT_VIDEO_EN (0x1c60 << 2) |
| #define VPU_ENCT_VIDEO_Y_SCL (0x1c61 << 2) |
| #define VPU_ENCT_VIDEO_PB_SCL (0x1c62 << 2) |
| #define VPU_ENCT_VIDEO_PR_SCL (0x1c63 << 2) |
| #define VPU_ENCT_VIDEO_Y_OFFST (0x1c64 << 2) |
| #define VPU_ENCT_VIDEO_PB_OFFST (0x1c65 << 2) |
| #define VPU_ENCT_VIDEO_PR_OFFST (0x1c66 << 2) |
| #define VPU_ENCT_VIDEO_MODE (0x1c67 << 2) |
| #define VPU_ENCT_VIDEO_MODE_ADV (0x1c68 << 2) |
| #define VPU_ENCT_DBG_PX_RST (0x1c69 << 2) |
| #define VPU_ENCT_DBG_LN_RST (0x1c6a << 2) |
| #define VPU_ENCT_DBG_PX_INT (0x1c6b << 2) |
| #define VPU_ENCT_DBG_LN_INT (0x1c6c << 2) |
| #define VPU_ENCT_VIDEO_YFP1_HTIME (0x1c6d << 2) |
| #define VPU_ENCT_VIDEO_YFP2_HTIME (0x1c6e << 2) |
| #define VPU_ENCT_VIDEO_YC_DLY (0x1c6f << 2) |
| #define VPU_ENCT_VIDEO_MAX_PXCNT (0x1c70 << 2) |
| #define VPU_ENCT_VIDEO_HAVON_END (0x1c71 << 2) |
| #define VPU_ENCT_VIDEO_HAVON_BEGIN (0x1c72 << 2) |
| #define VPU_ENCT_VIDEO_VAVON_ELINE (0x1c73 << 2) |
| #define VPU_ENCT_VIDEO_VAVON_BLINE (0x1c74 << 2) |
| #define VPU_ENCT_VIDEO_HSO_BEGIN (0x1c75 << 2) |
| #define VPU_ENCT_VIDEO_HSO_END (0x1c76 << 2) |
| #define VPU_ENCT_VIDEO_VSO_BEGIN (0x1c77 << 2) |
| #define VPU_ENCT_VIDEO_VSO_END (0x1c78 << 2) |
| #define VPU_ENCT_VIDEO_VSO_BLINE (0x1c79 << 2) |
| #define VPU_ENCT_VIDEO_VSO_ELINE (0x1c7a << 2) |
| #define VPU_ENCT_VIDEO_MAX_LNCNT (0x1c7b << 2) |
| #define VPU_ENCT_VIDEO_BLANKY_VAL (0x1c7c << 2) |
| #define VPU_ENCT_VIDEO_BLANKPB_VAL (0x1c7d << 2) |
| #define VPU_ENCT_VIDEO_BLANKPR_VAL (0x1c7e << 2) |
| #define VPU_ENCT_VIDEO_HOFFST (0x1c7f << 2) |
| #define VPU_ENCT_VIDEO_VOFFST (0x1c80 << 2) |
| #define VPU_ENCT_VIDEO_RGB_CTRL (0x1c81 << 2) |
| #define VPU_ENCT_VIDEO_FILT_CTRL (0x1c82 << 2) |
| #define VPU_ENCT_VIDEO_OFLD_VPEQ_OFST (0x1c83 << 2) |
| #define VPU_ENCT_VIDEO_OFLD_VOAV_OFST (0x1c84 << 2) |
| #define VPU_ENCT_VIDEO_MATRIX_CB (0x1c85 << 2) |
| #define VPU_ENCT_VIDEO_MATRIX_CR (0x1c86 << 2) |
| #define VPU_ENCT_VIDEO_RGBIN_CTRL (0x1c87 << 2) |
| #define VPU_ENCT_MAX_LINE_SWITCH_POINT (0x1c88 << 2) |
| #define VPU_ENCT_DACSEL_0 (0x1c89 << 2) |
| #define VPU_ENCT_DACSEL_1 (0x1c8a << 2) |
| #define VPU_ENCL_VFIFO2VD_CTL (0x1c90 << 2) |
| #define VPU_ENCL_VFIFO2VD_PIXEL_START (0x1c91 << 2) |
| #define VPU_ENCL_VFIFO2VD_PIXEL_END (0x1c92 << 2) |
| #define VPU_ENCL_VFIFO2VD_LINE_TOP_START (0x1c93 << 2) |
| #define VPU_ENCL_VFIFO2VD_LINE_TOP_END (0x1c94 << 2) |
| #define VPU_ENCL_VFIFO2VD_LINE_BOT_START (0x1c95 << 2) |
| #define VPU_ENCL_VFIFO2VD_LINE_BOT_END (0x1c96 << 2) |
| #define VPU_ENCL_VFIFO2VD_CTL2 (0x1c97 << 2) |
| #define VPU_ENCL_TST_EN (0x1c98 << 2) |
| #define VPU_ENCL_TST_MDSEL (0x1c99 << 2) |
| #define VPU_ENCL_TST_Y (0x1c9a << 2) |
| #define VPU_ENCL_TST_CB (0x1c9b << 2) |
| #define VPU_ENCL_TST_CR (0x1c9c << 2) |
| #define VPU_ENCL_TST_CLRBAR_STRT (0x1c9d << 2) |
| #define VPU_ENCL_TST_CLRBAR_WIDTH (0x1c9e << 2) |
| #define VPU_ENCL_TST_VDCNT_STSET (0x1c9f << 2) |
| #define VPU_ENCL_VIDEO_EN (0x1ca0 << 2) |
| #define VPU_ENCL_VIDEO_Y_SCL (0x1ca1 << 2) |
| #define VPU_ENCL_VIDEO_PB_SCL (0x1ca2 << 2) |
| #define VPU_ENCL_VIDEO_PR_SCL (0x1ca3 << 2) |
| #define VPU_ENCL_VIDEO_Y_OFFST (0x1ca4 << 2) |
| #define VPU_ENCL_VIDEO_PB_OFFST (0x1ca5 << 2) |
| #define VPU_ENCL_VIDEO_PR_OFFST (0x1ca6 << 2) |
| #define VPU_ENCL_VIDEO_MODE (0x1ca7 << 2) |
| #define VPU_ENCL_VIDEO_MODE_ADV (0x1ca8 << 2) |
| #define VPU_ENCL_DBG_PX_RST (0x1ca9 << 2) |
| #define VPU_ENCL_DBG_LN_RST (0x1caa << 2) |
| #define VPU_ENCL_DBG_PX_INT (0x1cab << 2) |
| #define VPU_ENCL_DBG_LN_INT (0x1cac << 2) |
| #define VPU_ENCL_VIDEO_YFP1_HTIME (0x1cad << 2) |
| #define VPU_ENCL_VIDEO_YFP2_HTIME (0x1cae << 2) |
| #define VPU_ENCL_VIDEO_YC_DLY (0x1caf << 2) |
| #define VPU_ENCL_VIDEO_MAX_PXCNT (0x1cb0 << 2) |
| #define VPU_ENCL_VIDEO_HAVON_END (0x1cb1 << 2) |
| #define VPU_ENCL_VIDEO_HAVON_BEGIN (0x1cb2 << 2) |
| #define VPU_ENCL_VIDEO_VAVON_ELINE (0x1cb3 << 2) |
| #define VPU_ENCL_VIDEO_VAVON_BLINE (0x1cb4 << 2) |
| #define VPU_ENCL_VIDEO_HSO_BEGIN (0x1cb5 << 2) |
| #define VPU_ENCL_VIDEO_HSO_END (0x1cb6 << 2) |
| #define VPU_ENCL_VIDEO_VSO_BEGIN (0x1cb7 << 2) |
| #define VPU_ENCL_VIDEO_VSO_END (0x1cb8 << 2) |
| #define VPU_ENCL_VIDEO_VSO_BLINE (0x1cb9 << 2) |
| #define VPU_ENCL_VIDEO_VSO_ELINE (0x1cba << 2) |
| #define VPU_ENCL_VIDEO_MAX_LNCNT (0x1cbb << 2) |
| #define VPU_ENCL_VIDEO_BLANKY_VAL (0x1cbc << 2) |
| #define VPU_ENCL_VIDEO_BLANKPB_VAL (0x1cbd << 2) |
| #define VPU_ENCL_VIDEO_BLANKPR_VAL (0x1cbe << 2) |
| #define VPU_ENCL_VIDEO_HOFFST (0x1cbf << 2) |
| #define VPU_ENCL_VIDEO_VOFFST (0x1cc0 << 2) |
| #define VPU_ENCL_VIDEO_RGB_CTRL (0x1cc1 << 2) |
| #define VPU_ENCL_VIDEO_FILT_CTRL (0x1cc2 << 2) |
| #define VPU_ENCL_VIDEO_OFLD_VPEQ_OFST (0x1cc3 << 2) |
| #define VPU_ENCL_VIDEO_OFLD_VOAV_OFST (0x1cc4 << 2) |
| #define VPU_ENCL_VIDEO_MATRIX_CB (0x1cc5 << 2) |
| #define VPU_ENCL_VIDEO_MATRIX_CR (0x1cc6 << 2) |
| #define VPU_ENCL_VIDEO_RGBIN_CTRL (0x1cc7 << 2) |
| #define VPU_ENCL_MAX_LINE_SWITCH_POINT (0x1cc8 << 2) |
| #define VPU_ENCL_DACSEL_0 (0x1cc9 << 2) |
| #define VPU_ENCL_DACSEL_1 (0x1cca << 2) |
| #define VPU_ENCI_INFO_READ (0x271c << 2) |
| #define VPU_ENCP_INFO_READ (0x271d << 2) |
| #define VPU_ENCT_INFO_READ (0x271e << 2) |
| #define VPU_ENCL_INFO_READ (0x271f << 2) |
| |
| #define VPU_VENC_SYNC_ROUTE (0x1b60 << 2) |
| #define VPU_VENC_VIDEO_EXSRC (0x1b61 << 2) |
| #define VPU_VENC_DVI_SETTING (0x1b62 << 2) |
| #define VPU_VENC_C656_CTRL (0x1b63 << 2) |
| #define VPU_VENC_UPSAMPLE_CTRL0 (0x1b64 << 2) |
| #define VPU_VENC_UPSAMPLE_CTRL1 (0x1b65 << 2) |
| #define VPU_VENC_UPSAMPLE_CTRL2 (0x1b66 << 2) |
| #define VPU_VENC_VIDEO_PROG_MODE (0x1b68 << 2) |
| #define VPU_VENC_ENCI_LINE (0x1b69 << 2) |
| #define VPU_VENC_ENCI_PIXEL (0x1b6a << 2) |
| #define VPU_VENC_ENCP_LINE (0x1b6b << 2) |
| #define VPU_VENC_ENCP_PIXEL (0x1b6c << 2) |
| #define VPU_VENC_STATA (0x1b6d << 2) |
| #define VPU_VENC_INTCTRL (0x1b6e << 2) |
| #define VPU_VENC_INTFLAG (0x1b6f << 2) |
| #define VPU_VENC_VIDEO_TST_EN (0x1b70 << 2) |
| #define VPU_VENC_VIDEO_TST_MDSEL (0x1b71 << 2) |
| #define VPU_VENC_VIDEO_TST_Y (0x1b72 << 2) |
| #define VPU_VENC_VIDEO_TST_CB (0x1b73 << 2) |
| #define VPU_VENC_VIDEO_TST_CR (0x1b74 << 2) |
| #define VPU_VENC_VIDEO_TST_CLRBAR_STRT (0x1b75 << 2) |
| #define VPU_VENC_VIDEO_TST_CLRBAR_WIDTH (0x1b76 << 2) |
| #define VPU_VENC_VIDEO_TST_VDCNT_STSET (0x1b77 << 2) |
| #define VPU_VENC_VDAC_DACSEL0 (0x1b78 << 2) |
| #define VPU_VENC_VDAC_DACSEL1 (0x1b79 << 2) |
| #define VPU_VENC_VDAC_DACSEL2 (0x1b7a << 2) |
| #define VPU_VENC_VDAC_DACSEL3 (0x1b7b << 2) |
| #define VPU_VENC_VDAC_DACSEL4 (0x1b7c << 2) |
| #define VPU_VENC_VDAC_DACSEL5 (0x1b7d << 2) |
| #define VPU_VENC_VDAC_SETTING (0x1b7e << 2) |
| #define VPU_VENC_VDAC_TST_VAL (0x1b7f << 2) |
| #define VPU_VENC_VDAC_DAC0_GAINCTRL (0x1bf0 << 2) |
| #define VPU_VENC_VDAC_DAC0_OFFSET (0x1bf1 << 2) |
| #define VPU_VENC_VDAC_DAC1_GAINCTRL (0x1bf2 << 2) |
| #define VPU_VENC_VDAC_DAC1_OFFSET (0x1bf3 << 2) |
| #define VPU_VENC_VDAC_DAC2_GAINCTRL (0x1bf4 << 2) |
| #define VPU_VENC_VDAC_DAC2_OFFSET (0x1bf5 << 2) |
| #define VPU_VENC_VDAC_DAC3_GAINCTRL (0x1bf6 << 2) |
| #define VPU_VENC_VDAC_DAC3_OFFSET (0x1bf7 << 2) |
| #define VPU_VENC_VDAC_DAC4_GAINCTRL (0x1bf8 << 2) |
| #define VPU_VENC_VDAC_DAC4_OFFSET (0x1bf9 << 2) |
| #define VPU_VENC_VDAC_DAC5_GAINCTRL (0x1bfa << 2) |
| #define VPU_VENC_VDAC_DAC5_OFFSET (0x1bfb << 2) |
| #define VPU_VENC_VDAC_FIFO_CTRL (0x1bfc << 2) |
| #define VPU_VENC_DVI_SETTING_MORE (0x1c51 << 2) |
| #define VPU_VENC_VDAC_DAC4_FILT_CTRL0 (0x1c54 << 2) |
| #define VPU_VENC_VDAC_DAC4_FILT_CTRL1 (0x1c55 << 2) |
| #define VPU_VENC_VDAC_DAC5_FILT_CTRL0 (0x1c56 << 2) |
| #define VPU_VENC_VDAC_DAC5_FILT_CTRL1 (0x1c57 << 2) |
| #define VPU_VENC_VDAC_DAC0_FILT_CTRL0 (0x1c58 << 2) |
| #define VPU_VENC_VDAC_DAC0_FILT_CTRL1 (0x1c59 << 2) |
| #define VPU_VENC_VDAC_DAC1_FILT_CTRL0 (0x1c5a << 2) |
| #define VPU_VENC_VDAC_DAC1_FILT_CTRL1 (0x1c5b << 2) |
| #define VPU_VENC_VDAC_DAC2_FILT_CTRL0 (0x1c5c << 2) |
| #define VPU_VENC_VDAC_DAC2_FILT_CTRL1 (0x1c5d << 2) |
| #define VPU_VENC_VDAC_DAC3_FILT_CTRL0 (0x1c5e << 2) |
| #define VPU_VENC_VDAC_DAC3_FILT_CTRL1 (0x1c5f << 2) |
| |
| #define VPU_OSD_PATH_MISC_CTRL (0x1a0e << 2) |
| #define VPU_OSD1_BLEND_SRC_CTRL (0x1dfd << 2) |
| #define VPU_OSD2_BLEND_SRC_CTRL (0x1dfe << 2) |
| #define VPU_OSD_BLENDO_H_START_END (0x1aa9 << 2) |
| #define VPU_OSD_BLENDO_V_START_END (0x1aaa << 2) |
| #define VPU_OSD_BLEND_GEN_CTRL0 (0x1aab << 2) |
| #define VPU_OSD_BLEND_GEN_CTRL1 (0x1aac << 2) |
| #define VPU_OSD_BLEND_DUMMY_DATA (0x1aad << 2) |
| #define VPU_OSD_BLEND_CURRENT_XY (0x1aae << 2) |
| #define VPU_OSD_DB_FLT_CTRL (0x3140 << 2) |
| #define VPU_OSD_DB_FLT_CTRL1 (0x3141 << 2) |
| #define VPU_OSD_DB_FLT_LUMA_THRD (0x3142 << 2) |
| #define VPU_OSD_DB_FLT_CHRM_THRD (0x3143 << 2) |
| #define VPU_OSD_DB_FLT_RANDLUT (0x3144 << 2) |
| #define VPU_OSD_DB_FLT_PXI_THRD (0x3145 << 2) |
| #define VPU_OSD_DB_FLT_SEED_Y (0x3146 << 2) |
| #define VPU_OSD_DB_FLT_SEED_U (0x3147 << 2) |
| #define VPU_OSD_DB_FLT_SEED_V (0x3148 << 2) |
| #define VPU_OSD_DB_FLT_SEED3 (0x3149 << 2) |
| #define VPU_OSD_DB_FLT_SEED4 (0x314a << 2) |
| #define VPU_OSD_DB_FLT_SEED5 (0x314b << 2) |
| #define VPU_OSD1_AFBCD_ENABLE (0x31a0 << 2) |
| #define VPU_OSD1_AFBCD_MODE (0x31a1 << 2) |
| #define VPU_OSD1_AFBCD_SIZE_IN (0x31a2 << 2) |
| #define VPU_OSD1_AFBCD_HDR_PTR (0x31a3 << 2) |
| #define VPU_OSD1_AFBCD_FRAME_PTR (0x31a4 << 2) |
| #define VPU_OSD1_AFBCD_CHROMA_PTR (0x31a5 << 2) |
| #define VPU_OSD1_AFBCD_CONV_CTRL (0x31a6 << 2) |
| #define VPU_OSD1_AFBCD_STATUS (0x31a8 << 2) |
| #define VPU_OSD1_AFBCD_PIXEL_HSCOPE (0x31a9 << 2) |
| #define VPU_OSD1_AFBCD_PIXEL_VSCOPE (0x31aa << 2) |
| |
| #define VPU_OSD1_MMC_CTRL (0x2701 << 2) |
| #define VPU_OSD2_MMC_CTRL (0x2702 << 2) |
| #define VPU_VD1_MMC_CTRL (0x2703 << 2) |
| #define VPU_VD2_MMC_CTRL (0x2704 << 2) |
| #define VPU_DI_IF1_MMC_CTRL (0x2705 << 2) |
| #define VPU_DI_MEM_MMC_CTRL (0x2706 << 2) |
| #define VPU_DI_INP_MMC_CTRL (0x2707 << 2) |
| #define VPU_DI_MTNRD_MMC_CTRL (0x2708 << 2) |
| #define VPU_DI_CHAN2_MMC_CTRL (0x2709 << 2) |
| #define VPU_DI_MTNWR_MMC_CTRL (0x270a << 2) |
| #define VPU_DI_NRWR_MMC_CTRL (0x270b << 2) |
| #define VPU_DI_DIWR_MMC_CTRL (0x270c << 2) |
| #define VPU_VDIN0_MMC_CTRL (0x270d << 2) |
| #define VPU_VDIN1_MMC_CTRL (0x270e << 2) |
| #define VPU_BT656_MMC_CTRL (0x270f << 2) |
| #define VPU_TVD3D_MMC_CTRL (0x2710 << 2) |
| #define VPU_TVDVBI_MMC_CTRL (0x2711 << 2) |
| #define VPU_VDIN_PRE_ARB_CTRL (0x2714 << 2) |
| #define VPU_VDISP_PRE_ARB_CTRL (0x2715 << 2) |
| #define VPU_VPUARB2_PRE_ARB_CTRL (0x2716 << 2) |
| #define VPU_OSD3_MMC_CTRL (0x2717 << 2) |
| #define VPU_OSD4_MMC_CTRL (0x2718 << 2) |
| #define VPU_VD3_MMC_CTRL (0x2719 << 2) |
| #define VPU_VIU_VENC_MUX_CTRL (0x271a << 2) |
| #define VPU_HDMI_SETTING (0x271b << 2) |
| #define VPU_SW_RESET (0x2720 << 2) |
| #define VPU_D2D3_MMC_CTRL (0x2721 << 2) |
| #define VPU_CONT_MMC_CTRL (0x2722 << 2) |
| #define VPU_CLK_GATE (0x2723 << 2) |
| #define VPU_RDMA_MMC_CTRL (0x2724 << 2) |
| #define VPU_MEM_PD_REG0 (0x2725 << 2) |
| #define VPU_MEM_PD_REG1 (0x2726 << 2) |
| #define VPU_HDMI_DATA_OVR (0x2727 << 2) |
| #define VPU_PROT1_MMC_CTRL (0x2728 << 2) |
| #define VPU_PROT2_MMC_CTRL (0x2729 << 2) |
| #define VPU_PROT3_MMC_CTRL (0x272a << 2) |
| #define VPU_ARB4_V1_MMC_CTRL (0x272b << 2) |
| #define VPU_ARB4_V2_MMC_CTRL (0x272c << 2) |
| #define VPU_MCVEC_MMC_CTRL (0x272d << 2) |
| #define VPU_MCINF_MMC_CTRL (0x272e << 2) |
| #define VPU_VPU_PWM_V0 (0x2730 << 2) |
| #define VPU_VPU_PWM_V1 (0x2731 << 2) |
| #define VPU_VPU_PWM_V2 (0x2732 << 2) |
| #define VPU_VPU_PWM_V3 (0x2733 << 2) |
| #define VPU_VPU_PWM_H0 (0x2734 << 2) |
| #define VPU_VPU_PWM_H1 (0x2735 << 2) |
| #define VPU_VPU_PWM_H2 (0x2736 << 2) |
| #define VPU_VPU_PWM_H3 (0x2737 << 2) |
| #define VPU_VPU_3D_SYNC1 (0x2738 << 2) |
| #define VPU_VPU_3D_SYNC2 (0x2739 << 2) |
| #define VPU_MISC_CTRL (0x2740 << 2) |
| #define VPU_ISP_GCLK_CTRL0 (0x2741 << 2) |
| #define VPU_ISP_GCLK_CTRL1 (0x2742 << 2) |
| #define VPU_HDMI_FMT_CTRL (0x2743 << 2) |
| #define VPU_VDIN_ASYNC_HOLD_CTRL (0x2744 << 2) |
| #define VPU_VDISP_ASYNC_HOLD_CTRL (0x2745 << 2) |
| #define VPU_VPUARB2_ASYNC_HOLD_CTRL (0x2746 << 2) |
| #define VPU_ARB_URG_CTRL (0x2747 << 2) |
| #define VPU_SECURE_DUMMY (0x2748 << 2) |
| #define VPU_VENCL_DITH_EN (0x2749 << 2) |
| #define VPU_422TO444_RST (0x274a << 2) |
| #define VPU_422TO444_CTRL0 (0x274b << 2) |
| #define VPU_422TO444_CTRL1 (0x274c << 2) |
| #define VPU_PROT1_CLK_GATE (0x2750 << 2) |
| #define VPU_PROT1_GEN_CNTL (0x2751 << 2) |
| #define VPU_PROT1_X_START_END (0x2752 << 2) |
| #define VPU_PROT1_Y_START_END (0x2753 << 2) |
| #define VPU_PROT1_Y_LEN_STEP (0x2754 << 2) |
| #define VPU_PROT1_RPT_LOOP (0x2755 << 2) |
| #define VPU_PROT1_RPT_PAT (0x2756 << 2) |
| #define VPU_PROT1_DDR (0x2757 << 2) |
| #define VPU_PROT1_RBUF_ROOM (0x2758 << 2) |
| #define VPU_PROT1_STAT_0 (0x2759 << 2) |
| #define VPU_PROT1_STAT_1 (0x275a << 2) |
| #define VPU_PROT1_STAT_2 (0x275b << 2) |
| #define VPU_PROT1_REQ_ONOFF (0x275c << 2) |
| #define VPU_PROT2_CLK_GATE (0x2760 << 2) |
| #define VPU_PROT2_GEN_CNTL (0x2761 << 2) |
| #define VPU_PROT2_X_START_END (0x2762 << 2) |
| #define VPU_PROT2_Y_START_END (0x2763 << 2) |
| #define VPU_PROT2_Y_LEN_STEP (0x2764 << 2) |
| #define VPU_PROT2_RPT_LOOP (0x2765 << 2) |
| #define VPU_PROT2_RPT_PAT (0x2766 << 2) |
| #define VPU_PROT2_DDR (0x2767 << 2) |
| #define VPU_PROT2_RBUF_ROOM (0x2768 << 2) |
| #define VPU_PROT2_STAT_0 (0x2769 << 2) |
| #define VPU_PROT2_STAT_1 (0x276a << 2) |
| #define VPU_PROT2_STAT_2 (0x276b << 2) |
| #define VPU_PROT2_REQ_ONOFF (0x276c << 2) |
| #define VPU_PROT3_CLK_GATE (0x2770 << 2) |
| #define VPU_PROT3_GEN_CNTL (0x2771 << 2) |
| #define VPU_PROT3_X_START_END (0x2772 << 2) |
| #define VPU_PROT3_Y_START_END (0x2773 << 2) |
| #define VPU_PROT3_Y_LEN_STEP (0x2774 << 2) |
| #define VPU_PROT3_RPT_LOOP (0x2775 << 2) |
| #define VPU_PROT3_RPT_PAT (0x2776 << 2) |
| #define VPU_PROT3_DDR (0x2777 << 2) |
| #define VPU_PROT3_RBUF_ROOM (0x2778 << 2) |
| #define VPU_PROT3_STAT_0 (0x2779 << 2) |
| #define VPU_PROT3_STAT_1 (0x277a << 2) |
| #define VPU_PROT3_STAT_2 (0x277b << 2) |
| #define VPU_PROT3_REQ_ONOFF (0x277c << 2) |
| #define VPU_VIU2VDIN_HDN_CTRL (0x2780 << 2) |
| #define VPU_VIU_ASYNC_MASK (0x2781 << 2) |
| #define VPU_RDARB_MODE_L1C1 (0x2790 << 2) |
| #define VPU_RDARB_REQEN_SLV_L1C1 (0x2791 << 2) |
| #define VPU_RDARB_WEIGH0_SLV_L1C1 (0x2792 << 2) |
| #define VPU_RDARB_WEIGH1_SLV_L1C1 (0x2793 << 2) |
| #define VPU_WRARB_MODE_L1C1 (0x2794 << 2) |
| #define VPU_WRARB_REQEN_SLV_L1C1 (0x2795 << 2) |
| #define VPU_WRARB_WEIGH0_SLV_L1C1 (0x2796 << 2) |
| #define VPU_WRARB_WEIGH1_SLV_L1C1 (0x2797 << 2) |
| #define VPU_RDWR_ARB_STATUS_L1C1 (0x2798 << 2) |
| #define VPU_RDARB_MODE_L1C2 (0x2799 << 2) |
| #define VPU_RDARB_REQEN_SLV_L1C2 (0x279a << 2) |
| #define VPU_RDARB_WEIGH0_SLV_L1C2 (0x279b << 2) |
| #define VPU_RDWR_ARB_STATUS_L1C2 (0x279c << 2) |
| #define VPU_RDARB_MODE_L2C1 (0x279d << 2) |
| #define VPU_RDARB_REQEN_SLV_L2C1 (0x279e << 2) |
| #define VPU_RDARB_WEIGH0_SLV_L2C1 (0x279f << 2) |
| #define VPU_RDARB_WEIGH1_SLV_L2C1 (0x27a0 << 2) |
| #define VPU_RDWR_ARB_STATUS_L2C1 (0x27a1 << 2) |
| #define VPU_WRARB_MODE_L2C1 (0x27a2 << 2) |
| #define VPU_WRARB_REQEN_SLV_L2C1 (0x27a3 << 2) |
| #define VPU_WRARB_WEIGH0_SLV_L2C1 (0x27a4 << 2) |
| #define VPU_ASYNC_RD_MODE0 (0x27a5 << 2) |
| #define VPU_ASYNC_RD_MODE1 (0x27a6 << 2) |
| #define VPU_ASYNC_RD_MODE2 (0x27a7 << 2) |
| #define VPU_ASYNC_RD_MODE3 (0x27a8 << 2) |
| #define VPU_ASYNC_RD_MODE4 (0x27a9 << 2) |
| #define VPU_ASYNC_WR_MODE0 (0x27aa << 2) |
| #define VPU_ASYNC_WR_MODE1 (0x27ab << 2) |
| #define VPU_ASYNC_WR_MODE2 (0x27ac << 2) |
| #define VPU_ASYNC_STAT (0x27ad << 2) |
| #define VPU_WRARB_MODE_L1C2 (0x27ae << 2) |
| #define VPU_WRARB_REQEN_SLV_L1C2 (0x27af << 2) |
| #define VPU_WRARB_WEIGH0_SLV_L1C2 (0x27b0 << 2) |
| #define VPU_WRARB_WEIGH1_SLV_L1C2 (0x27b1 << 2) |
| #define VPU_RDARB_WEIGH1_SLV_L1C2 (0x27b2 << 2) |
| #define VPU_ARB_DBG_CTRL_L1C1 (0x27b3 << 2) |
| #define VPU_ARB_DBG_STAT_L1C1 (0x27b4 << 2) |
| #define VPU_ARB_DBG_CTRL_L1C2 (0x27b5 << 2) |
| #define VPU_ARB_DBG_STAT_L1C2 (0x27b6 << 2) |
| #define VPU_ARB_DBG_CTRL_L2C1 (0x27b7 << 2) |
| #define VPU_ARB_DBG_STAT_L2C1 (0x27b8 << 2) |
| #define VPU_ARB_PATH_CTRL (0x27b9 << 2) |
| #define VPU_ARB_PATH_MAP00 (0x27ba << 2) |
| #define VPU_ARB_PATH_MAP01 (0x27bb << 2) |
| #define VPU_ARB_PATH_MAP02 (0x27bc << 2) |
| #define VPU_ARB_PATH_MAP03 (0x27bd << 2) |
| #define VPU_ARB_PATH_MAP10 (0x27be << 2) |
| #define VPU_ARB_PATH_MAP11 (0x27bf << 2) |
| #define VPU_ARB_PATH_MAP12 (0x27c0 << 2) |
| #define VPU_ARB_PATH_MAP13 (0x27c1 << 2) |
| #define VPU_VENCL_DITH_CTRL (0x27e0 << 2) |
| #define VPU_VENCL_DITH_LUT_1 (0x27e1 << 2) |
| #define VPU_VENCL_DITH_LUT_2 (0x27e2 << 2) |
| #define VPU_VENCL_DITH_LUT_3 (0x27e3 << 2) |
| #define VPU_VENCL_DITH_LUT_4 (0x27e4 << 2) |
| #define VPU_VENCL_DITH_LUT_5 (0x27e5 << 2) |
| #define VPU_VENCL_DITH_LUT_6 (0x27e6 << 2) |
| #define VPU_VENCL_DITH_LUT_7 (0x27e7 << 2) |
| #define VPU_VENCL_DITH_LUT_8 (0x27e8 << 2) |
| #define VPU_VENCL_DITH_LUT_9 (0x27e9 << 2) |
| #define VPU_VENCL_DITH_LUT_10 (0x27ea << 2) |
| #define VPU_VENCL_DITH_LUT_11 (0x27eb << 2) |
| #define VPU_VENCL_DITH_LUT_12 (0x27ec << 2) |
| #define VPU_HDMI_DITH_01_04 (0x27f0 << 2) |
| #define VPU_HDMI_DITH_01_15 (0x27f1 << 2) |
| #define VPU_HDMI_DITH_01_26 (0x27f2 << 2) |
| #define VPU_HDMI_DITH_01_37 (0x27f3 << 2) |
| #define VPU_HDMI_DITH_10_04 (0x27f4 << 2) |
| #define VPU_HDMI_DITH_10_15 (0x27f5 << 2) |
| #define VPU_HDMI_DITH_10_26 (0x27f6 << 2) |
| #define VPU_HDMI_DITH_10_37 (0x27f7 << 2) |
| #define VPU_HDMI_DITH_11_04 (0x27f8 << 2) |
| #define VPU_HDMI_DITH_11_15 (0x27f9 << 2) |
| #define VPU_HDMI_DITH_11_26 (0x27fa << 2) |
| #define VPU_HDMI_DITH_11_37 (0x27fb << 2) |
| #define VPU_HDMI_DITH_CNTL (0x27fc << 2) |
| #define VPU_VLOCK_CTRL (0x3000 << 2) |
| #define VPU_VLOCK_MISC_CTRL (0x3001 << 2) |
| #define VPU_VLOCK_LOOP0_ACCUM_LMT (0x3002 << 2) |
| #define VPU_VLOCK_LOOP0_CTRL0 (0x3003 << 2) |
| #define VPU_VLOCK_LOOP1_CTRL0 (0x3004 << 2) |
| #define VPU_VLOCK_LOOP1_IMISSYNC_MAX (0x3005 << 2) |
| #define VPU_VLOCK_LOOP1_IMISSYNC_MIN (0x3006 << 2) |
| #define VPU_VLOCK_OVWRITE_ACCUM0 (0x3007 << 2) |
| #define VPU_VLOCK_OVWRITE_ACCUM1 (0x3008 << 2) |
| #define VPU_VLOCK_OUTPUT0_CAPT_LMT (0x3009 << 2) |
| #define VPU_VLOCK_OUTPUT0_PLL_LMT (0x300a << 2) |
| #define VPU_VLOCK_OUTPUT1_CAPT_LMT (0x300b << 2) |
| #define VPU_VLOCK_OUTPUT1_PLL_LMT (0x300c << 2) |
| #define VPU_VLOCK_LOOP1_PHSDIF_TGT (0x300d << 2) |
| #define VPU_VLOCK_RO_LOOP0_ACCUM (0x300e << 2) |
| #define VPU_VLOCK_RO_LOOP1_ACCUM (0x300f << 2) |
| #define VPU_VLOCK_OROW_OCOL_MAX (0x3010 << 2) |
| #define VPU_VLOCK_RO_VS_I_DIST (0x3011 << 2) |
| #define VPU_VLOCK_RO_VS_O_DIST (0x3012 << 2) |
| #define VPU_VLOCK_RO_LINE_PIX_ADJ (0x3013 << 2) |
| #define VPU_VLOCK_RO_OUTPUT_00_01 (0x3014 << 2) |
| #define VPU_VLOCK_RO_OUTPUT_10_11 (0x3015 << 2) |
| #define VPU_VLOCK_MX4096 (0x3016 << 2) |
| #define VPU_VLOCK_STBDET_WIN0_WIN1 (0x3017 << 2) |
| #define VPU_VLOCK_STBDET_CLP (0x3018 << 2) |
| #define VPU_VLOCK_STBDET_ABS_WIN0 (0x3019 << 2) |
| #define VPU_VLOCK_STBDET_ABS_WIN1 (0x301a << 2) |
| #define VPU_VLOCK_STBDET_SGN_WIN0 (0x301b << 2) |
| #define VPU_VLOCK_STBDET_SGN_WIN1 (0x301c << 2) |
| #define VPU_VLOCK_ADJ_EN_SYNC_CTRL (0x301d << 2) |
| #define VPU_VLOCK_GCLK_EN (0x301e << 2) |
| #define VPU_VLOCK_LOOP1_ACCUM_LMT (0x301f << 2) |
| #define VPU_VLOCK_RO_M_INT_FRAC (0x3020 << 2) |
