[zircon][amlogic][sdhci] Clear all the registers after a reset
After a reset, clear all the registers and reinitialize them to default
values. Without this, device is in idle state but the timing used to
communincate with the device is not the way its supposed to be and so
the commands fail with CRC errors.
Change-Id: Ia9edae7c743ab474713308d2979787e3c5c75b52
diff --git a/system/dev/block/aml-sd-emmc/aml-sd-emmc.c b/system/dev/block/aml-sd-emmc/aml-sd-emmc.c
index 044c3c0..a360ed0 100644
--- a/system/dev/block/aml-sd-emmc/aml-sd-emmc.c
+++ b/system/dev/block/aml-sd-emmc/aml-sd-emmc.c
@@ -221,9 +221,32 @@
return ZX_OK;
}
+static void aml_sd_emmc_init_regs(aml_sd_emmc_t* dev) {
+ aml_sd_emmc_regs_t* regs = dev->regs;
+ uint32_t config = 0;
+ uint32_t clk_val = 0;
+ update_bits(&config, AML_SD_EMMC_CFG_BL_LEN_MASK, AML_SD_EMMC_CFG_BL_LEN_LOC,
+ AML_SD_EMMC_DEFAULT_BL_LEN);
+ update_bits(&config, AML_SD_EMMC_CFG_RESP_TIMEOUT_MASK, AML_SD_EMMC_CFG_RESP_TIMEOUT_LOC,
+ AML_SD_EMMC_DEFAULT_RESP_TIMEOUT);
+ update_bits(&config, AML_SD_EMMC_CFG_RC_CC_MASK, AML_SD_EMMC_CFG_RC_CC_LOC,
+ AML_SD_EMMC_DEFAULT_RC_CC);
+ update_bits(&config, AML_SD_EMMC_CFG_BUS_WIDTH_MASK, AML_SD_EMMC_CFG_BUS_WIDTH_LOC,
+ AML_SD_EMMC_CFG_BUS_WIDTH_1BIT);
+ update_bits(&clk_val, AML_SD_EMMC_CLOCK_CFG_CO_PHASE_MASK,
+ AML_SD_EMMC_CLOCK_CFG_CO_PHASE_LOC, AML_SD_EMMC_DEFAULT_CLK_CORE_PHASE);
+ update_bits(&clk_val, AML_SD_EMMC_CLOCK_CFG_SRC_MASK, AML_SD_EMMC_CLOCK_CFG_SRC_LOC,
+ AML_SD_EMMC_DEFAULT_CLK_SRC);
+ update_bits(&clk_val, AML_SD_EMMC_CLOCK_CFG_DIV_MASK, AML_SD_EMMC_CLOCK_CFG_DIV_LOC,
+ AML_SD_EMMC_DEFAULT_CLK_DIV);
+ clk_val |= AML_SD_EMMC_CLOCK_CFG_ALWAYS_ON;
+
+ regs->sd_emmc_clock = clk_val;
+ regs->sd_emmc_cfg = config;
+}
+
static void aml_sd_emmc_hw_reset(void* ctx) {
aml_sd_emmc_t *dev = (aml_sd_emmc_t *)ctx;
- aml_sd_emmc_regs_t* regs = dev->regs;
if (dev->gpio_count == 1) {
//Currently we only have 1 gpio
gpio_config(&dev->gpio, 0, GPIO_DIR_OUT);
@@ -231,26 +254,7 @@
usleep(10 * 1000);
gpio_write(&dev->gpio, 0, 1);
}
- uint32_t config = regs->sd_emmc_cfg;
- uint32_t clk_val = regs->sd_emmc_clock;
-
- update_bits(&config, AML_SD_EMMC_CFG_BL_LEN_MASK, AML_SD_EMMC_CFG_BL_LEN_LOC, 9);
- update_bits(&config, AML_SD_EMMC_CFG_RESP_TIMEOUT_MASK, AML_SD_EMMC_CFG_RESP_TIMEOUT_LOC, 8);
- update_bits(&config, AML_SD_EMMC_CFG_RC_CC_MASK, AML_SD_EMMC_CFG_RC_CC_LOC, 4);
-
- update_bits(&clk_val, AML_SD_EMMC_CLOCK_CFG_CO_PHASE_MASK,
- AML_SD_EMMC_CLOCK_CFG_CO_PHASE_LOC, 2);
- update_bits(&clk_val, AML_SD_EMMC_CLOCK_CFG_RX_PHASE_MASK,
- AML_SD_EMMC_CLOCK_CFG_RX_PHASE_LOC, 0);
- update_bits(&clk_val, AML_SD_EMMC_CLOCK_CFG_RX_DELAY_MASK, AML_SD_EMMC_CLOCK_CFG_RX_DELAY_LOC,
- 0);
- clk_val |= AML_SD_EMMC_CLOCK_CFG_ALWAYS_ON;
-
- regs->sd_emmc_clock = clk_val;
- regs->sd_emmc_cfg = config;
-
- aml_sd_emmc_set_bus_width(ctx, SDMMC_BUS_WIDTH_1);
- aml_sd_emmc_set_bus_freq(ctx, AML_SD_EMMC_MIN_FREQ - 1);
+ aml_sd_emmc_init_regs(dev);
}
static zx_status_t aml_sd_emmc_set_bus_timing(void* ctx, sdmmc_timing_t timing) {
diff --git a/system/dev/soc/amlogic/include/soc/aml-common/aml-sd-emmc.h b/system/dev/soc/amlogic/include/soc/aml-common/aml-sd-emmc.h
index c60bf6f..d69bc15 100644
--- a/system/dev/soc/amlogic/include/soc/aml-common/aml-sd-emmc.h
+++ b/system/dev/soc/amlogic/include/soc/aml-common/aml-sd-emmc.h
@@ -20,7 +20,7 @@
return (x & mask) ? 1 : 0;
}
-//From EMMC Design Logic documentation provided by AMLOGIC
+//From EMMC Design documentation provided by AMLOGIC
#define AML_SD_EMMC_IRQ_ALL_CLEAR 0x3fff
#define AML_SD_EMMC_MIN_FREQ 400000 //400KHz
#define AML_SD_EMMC_MAX_FREQ 40000000
@@ -31,6 +31,14 @@
//~Min freq attainable with DIV2 Src
#define AML_SD_EMMC_FCLK_DIV2_MIN_FREQ 20000000 //20MHz
+//Default values after reset.EMMC Design Docs by AMLOGIC: PG 56
+#define AML_SD_EMMC_DEFAULT_BL_LEN 9 //512 bytes
+#define AML_SD_EMMC_DEFAULT_RESP_TIMEOUT 8 //256 core clock cycles
+#define AML_SD_EMMC_DEFAULT_RC_CC 4 //16 core clock cycles
+#define AML_SD_EMMC_DEFAULT_CLK_SRC 0 //24MHz
+#define AML_SD_EMMC_DEFAULT_CLK_DIV 60 //Defaults to 400KHz
+#define AML_SD_EMMC_DEFAULT_CLK_CORE_PHASE 2
+
typedef struct {
volatile uint32_t sd_emmc_clock; // 0x00
#define AML_SD_EMMC_CLOCK_CFG_DIV_LOC 0
