commit f1e524c2815d47887e19b255baaca56e8b7c6de8
author Andres Oportus <andresoportus@google.com> Fri Dec 14 13:24:15 2018 -0800
committer CQ bot account: commit-bot@chromium.org <commit-bot@chromium.org> Fri Dec 14 22:04:43 2018 +0000
tree c87a4d8fa292c13fda2e68b8e996f3d1feeff4e4
parent fb2f60763e796be20d9224941441adb92ceea6f6

[mt8167s_ref] Add comments to clarify SOC interrupts polarity inversions

Test: builds (only comments added)
Change-Id: I4b348b972ed4e7479d9333bca86dc9f7fb9dfab3

system/dev/board/mt8167s_ref/mt8167-soc.cpp

diff --git a/system/dev/board/mt8167s_ref/mt8167-soc.cpp b/system/dev/board/mt8167s_ref/mt8167-soc.cpp
index 1f9c859..f809218 100644
--- a/system/dev/board/mt8167s_ref/mt8167-soc.cpp
+++ b/system/dev/board/mt8167s_ref/mt8167-soc.cpp
@@ -33,21 +33,22 @@
     static constexpr bool L = 1;
     static constexpr bool H = 0;
     static constexpr bool R = 0;
+
     static const bool spi_polarities[] = {
-        L, L, L, L, R, R, R, R, L, L, L, L, R, R, R, R,
-        L, L, L, L, R, R, R, R, L, L, L, L, R, R, R, R,
-        L, L, L, L, R, R, R, R, L, L, L, L, R, R, R, R,
-        L, R, L, L, L, L, R, R, R, R, R, R, R, R, R, L,
-        H, H, H, H, H, H, H, H, L, L, R, L, L, L, L, L,
-        L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L,
-        L, L, L, L, L, L, L, L, L, H, H, L, H, L, L, L,
-        L, L, L, L, H, L, L, L, L, L, L, L, L, L, L, L,
-        L, L, L, L, L, H, H, L, L, L, L, L, L, L, L, L,
-        L, L, L, L, R, L, L, L, L, L, L, L, L, L, L, L,
-        L, R, L, L, L, L, L, L, L, L, R, L, L, L, L, L,
-        L, L, L, L, L, L, L, L, L, H, L, L, L, L, L, R,
-        R, R, L, L, L, L, L, L, L, L, L, R, L, H, H, H,
-        H, L, L, L, R, R, L, H, H, H, H
+        L, L, L, L, R, R, R, R, L, L, L, L, R, R, R, R, // 32 (first interrupt in the line).
+        L, L, L, L, R, R, R, R, L, L, L, L, R, R, R, R, // 48.
+        L, L, L, L, R, R, R, R, L, L, L, L, R, R, R, R, // 64.
+        L, R, L, L, L, L, R, R, R, R, R, R, R, R, R, L, // 80.
+        H, H, H, H, H, H, H, H, L, L, R, L, L, L, L, L, // 96.
+        L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, // 112.
+        L, L, L, L, L, L, L, L, L, H, H, L, H, L, L, L, // 128.
+        L, L, L, L, H, L, L, L, L, L, L, L, L, L, L, L, // 144.
+        L, L, L, L, L, H, H, L, L, L, L, L, L, L, L, L, // 160.
+        L, L, L, L, R, L, L, L, L, L, L, L, L, L, L, L, // 176.
+        L, R, L, L, L, L, L, L, L, L, R, L, L, L, L, L, // 192.
+        L, L, L, L, L, L, L, L, L, H, L, L, L, L, L, R, // 208.
+        R, R, L, L, L, L, L, L, L, L, L, R, L, H, H, H, // 224.
+        H, L, L, L, R, R, L, H, H, H, H                 // 240 (first is 240, last is 250).
     };
 
     // Start from interrupt 32 (first SPI after 32 PPIs)