[api] Make zircon/syscalls/pci.h enums readability compliant
Test: CQ
Change-Id: Ic0a311b683eb400746ce1ab7dad7ca01b3e66345
diff --git a/kernel/syscalls/ddk_pci.cpp b/kernel/syscalls/ddk_pci.cpp
index 1f7332c..322176f 100644
--- a/kernel/syscalls/ddk_pci.cpp
+++ b/kernel/syscalls/ddk_pci.cpp
@@ -503,7 +503,7 @@
// back to the caller as a VMO.
zx_pci_bar_t bar = {};
bar.size = info->size;
- bar.type = (info->is_mmio) ? PCI_BAR_TYPE_MMIO : PCI_BAR_TYPE_PIO;
+ bar.type = (info->is_mmio) ? ZX_PCI_BAR_TYPE_MMIO : ZX_PCI_BAR_TYPE_PIO;
// MMIO based bars are passed back using a VMO. If we end up creating one here
// without errors then later a handle will be passed back to the caller.
diff --git a/system/dev/audio/intel-hda/controller/intel-hda-controller-init.cpp b/system/dev/audio/intel-hda/controller/intel-hda-controller-init.cpp
index 2e217f1..d517ff2 100644
--- a/system/dev/audio/intel-hda/controller/intel-hda-controller-init.cpp
+++ b/system/dev/audio/intel-hda/controller/intel-hda-controller-init.cpp
@@ -197,9 +197,9 @@
return res;
}
- if (bar_info.type != PCI_BAR_TYPE_MMIO) {
+ if (bar_info.type != ZX_PCI_BAR_TYPE_MMIO) {
LOG(ERROR, "Bad register window type (expected %u got %u)\n",
- PCI_BAR_TYPE_MMIO, bar_info.type);
+ ZX_PCI_BAR_TYPE_MMIO, bar_info.type);
return ZX_ERR_INTERNAL;
}
diff --git a/system/dev/audio/intel-hda/controller/intel-hda-dsp.cpp b/system/dev/audio/intel-hda/controller/intel-hda-dsp.cpp
index 7225814..1497391 100644
--- a/system/dev/audio/intel-hda/controller/intel-hda-dsp.cpp
+++ b/system/dev/audio/intel-hda/controller/intel-hda-dsp.cpp
@@ -245,9 +245,9 @@
return res;
}
- if (bar_info.type != PCI_BAR_TYPE_MMIO) {
+ if (bar_info.type != ZX_PCI_BAR_TYPE_MMIO) {
LOG(ERROR, "Bad register window type (expected %u got %u)\n",
- PCI_BAR_TYPE_MMIO, bar_info.type);
+ ZX_PCI_BAR_TYPE_MMIO, bar_info.type);
return ZX_ERR_INTERNAL;
}
diff --git a/system/dev/bus/pci/proxy.c b/system/dev/bus/pci/proxy.c
index f4863f6..2d00114 100644
--- a/system/dev/bus/pci/proxy.c
+++ b/system/dev/bus/pci/proxy.c
@@ -174,7 +174,7 @@
if (st == ZX_OK) {
// Grab the payload and copy the handle over if one was passed back to us
*out_bar = resp.bar;
- if (out_bar->type == PCI_BAR_TYPE_PIO) {
+ if (out_bar->type == ZX_PCI_BAR_TYPE_PIO) {
#if __x86_64__
// x86 PIO space access requires permission in the I/O bitmap
// TODO: this is the last remaining use of get_root_resource in pci
@@ -213,7 +213,7 @@
}
// TODO(cja): PIO may be mappable on non-x86 architectures
- if (bar.type == PCI_BAR_TYPE_PIO || bar.handle == ZX_HANDLE_INVALID) {
+ if (bar.type == ZX_PCI_BAR_TYPE_PIO || bar.handle == ZX_HANDLE_INVALID) {
return ZX_ERR_WRONG_TYPE;
}
diff --git a/system/dev/bus/virtio/backends/pci_legacy.cpp b/system/dev/bus/virtio/backends/pci_legacy.cpp
index 360f838..50c2cfc 100644
--- a/system/dev/bus/virtio/backends/pci_legacy.cpp
+++ b/system/dev/bus/virtio/backends/pci_legacy.cpp
@@ -47,7 +47,7 @@
return status;
}
- if (bar0.type != PCI_BAR_TYPE_PIO) {
+ if (bar0.type != ZX_PCI_BAR_TYPE_PIO) {
return ZX_ERR_WRONG_TYPE;
}
diff --git a/system/public/zircon/syscalls/pci.h b/system/public/zircon/syscalls/pci.h
index 44aea32..6d5ccc0 100644
--- a/system/public/zircon/syscalls/pci.h
+++ b/system/public/zircon/syscalls/pci.h
@@ -17,11 +17,10 @@
// in the case of an MMIO bar, as well as a PIO addr/size pair for the memory region
// to access if a PIO bar. In the latter case, the protocol will acquire the appropriate
// permissions for the process to write to that PIO region on that architecture.
-typedef enum {
- PCI_BAR_TYPE_UNUSED = 0,
- PCI_BAR_TYPE_MMIO,
- PCI_BAR_TYPE_PIO,
-} zx_pci_bar_types_t;
+typedef uint32_t zx_pci_bar_types_t;
+#define ZX_PCI_BAR_TYPE_UNUSED ((zx_pci_bar_types_t) 0u)
+#define ZX_PCI_BAR_TYPE_MMIO ((zx_pci_bar_types_t) 1u)
+#define ZX_PCI_BAR_TYPE_PIO ((zx_pci_bar_types_t) 2u)
// TODO(cja): This makes some assumptions that anything in an arch's PIO region
// is going to be defined as a base address and size. This will need to be
@@ -106,11 +105,10 @@
sizeof(zx_pci_init_arg_t))
// Enum used to select PCIe IRQ modes
-typedef enum {
- ZX_PCIE_IRQ_MODE_DISABLED = 0,
- ZX_PCIE_IRQ_MODE_LEGACY = 1,
- ZX_PCIE_IRQ_MODE_MSI = 2,
- ZX_PCIE_IRQ_MODE_MSI_X = 3,
-} zx_pci_irq_mode_t;
+typedef uint32_t zx_pci_irq_mode_t;
+#define ZX_PCIE_IRQ_MODE_DISABLED ((zx_pci_irq_mode_t) 0u)
+#define ZX_PCIE_IRQ_MODE_LEGACY ((zx_pci_irq_mode_t) 1u)
+#define ZX_PCIE_IRQ_MODE_MSI ((zx_pci_irq_mode_t) 2u)
+#define ZX_PCIE_IRQ_MODE_MSI_X ((zx_pci_irq_mode_t) 3u)
__END_CDECLS
