[amlogic][rawnand] clang-format all source files.
Change-Id: Ic6c5442c765b52d165fe6c296f0cab0ad489fc57
diff --git a/system/dev/rawnand/aml-rawnand/aml-rawnand.c b/system/dev/rawnand/aml-rawnand/aml-rawnand.c
index fccd779..4ce71a0 100644
--- a/system/dev/rawnand/aml-rawnand/aml-rawnand.c
+++ b/system/dev/rawnand/aml-rawnand/aml-rawnand.c
@@ -2,28 +2,28 @@
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
-#include <stdint.h>
-#include <time.h>
-#include <stdlib.h>
#include <errno.h>
-#include <unistd.h>
#include <fcntl.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <time.h>
+#include <unistd.h>
#include <bits/limits.h>
#include <ddk/binding.h>
#include <ddk/debug.h>
#include <ddk/device.h>
+#include <ddk/io-buffer.h>
#include <ddk/protocol/platform-defs.h>
#include <ddk/protocol/platform-device.h>
#include <ddk/protocol/rawnand.h>
-#include <ddk/io-buffer.h>
#include <hw/reg.h>
+#include <sync/completion.h>
#include <zircon/assert.h>
+#include <zircon/status.h>
#include <zircon/threads.h>
#include <zircon/types.h>
-#include <zircon/status.h>
-#include <sync/completion.h>
#include <string.h>
@@ -37,18 +37,17 @@
8,
2,
/* The 2 following values are overwritten by page0 contents */
- 1, /* rand-mode is 1 for page0 */
- AML_ECC_BCH60_1K, /* This is the BCH setting for page0 */
+ 1, /* rand-mode is 1 for page0 */
+ AML_ECC_BCH60_1K, /* This is the BCH setting for page0 */
};
-static void aml_cmd_ctrl(void *ctx,
+static void aml_cmd_ctrl(void* ctx,
int32_t cmd, uint32_t ctrl);
-static uint8_t aml_read_byte(void *ctx);
+static uint8_t aml_read_byte(void* ctx);
static zx_status_t aml_nand_init(aml_raw_nand_t* raw_nand);
-static const char *aml_ecc_string(uint32_t ecc_mode)
-{
- const char *s;
+static const char* aml_ecc_string(uint32_t ecc_mode) {
+ const char* s;
switch (ecc_mode) {
case AML_ECC_BCH8:
@@ -79,8 +78,7 @@
return s;
}
-uint32_t aml_get_ecc_pagesize(aml_raw_nand_t *raw_nand, uint32_t ecc_mode)
-{
+uint32_t aml_get_ecc_pagesize(aml_raw_nand_t* raw_nand, uint32_t ecc_mode) {
uint32_t ecc_page;
switch (ecc_mode) {
@@ -102,24 +100,22 @@
return ecc_page;
}
-static void aml_cmd_idle(aml_raw_nand_t *raw_nand, uint32_t time)
-{
+static void aml_cmd_idle(aml_raw_nand_t* raw_nand, uint32_t time) {
uint32_t cmd = 0;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
cmd = raw_nand->chip_select | AML_CMD_IDLE | (time & 0x3ff);
writel(cmd, reg + P_NAND_CMD);
}
-static zx_status_t aml_wait_cmd_finish(aml_raw_nand_t *raw_nand,
- unsigned int timeout_ms)
-{
+static zx_status_t aml_wait_cmd_finish(aml_raw_nand_t* raw_nand,
+ unsigned int timeout_ms) {
uint32_t cmd_size = 0;
zx_status_t ret = ZX_OK;
uint64_t total_time = 0;
uint32_t numcmds;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
/* wait until cmd fifo is empty */
@@ -140,42 +136,38 @@
return ret;
}
-static void aml_cmd_seed(aml_raw_nand_t *raw_nand, uint32_t seed)
-{
+static void aml_cmd_seed(aml_raw_nand_t* raw_nand, uint32_t seed) {
uint32_t cmd;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
cmd = AML_CMD_SEED | (0xc2 + (seed & 0x7fff));
writel(cmd, reg + P_NAND_CMD);
}
-static void aml_cmd_n2m(aml_raw_nand_t *raw_nand, uint32_t ecc_pages,
- uint32_t ecc_pagesize)
-{
+static void aml_cmd_n2m(aml_raw_nand_t* raw_nand, uint32_t ecc_pages,
+ uint32_t ecc_pagesize) {
uint32_t cmd;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
cmd = CMDRWGEN(AML_CMD_N2M,
raw_nand->controller_params.rand_mode,
raw_nand->controller_params.bch_mode,
0,
- ecc_pagesize,
+ ecc_pagesize,
ecc_pages);
writel(cmd, reg + P_NAND_CMD);
}
-static void aml_cmd_m2n_page0(aml_raw_nand_t *raw_nand)
-{
+static void aml_cmd_m2n_page0(aml_raw_nand_t* raw_nand) {
/* TODO */
}
-static void aml_cmd_m2n(aml_raw_nand_t *raw_nand, uint32_t ecc_pages,
- uint32_t ecc_pagesize)
-{
+static void aml_cmd_m2n(aml_raw_nand_t* raw_nand, uint32_t ecc_pages,
+ uint32_t ecc_pagesize) {
uint32_t cmd;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
cmd = CMDRWGEN(AML_CMD_M2N,
@@ -186,10 +178,9 @@
writel(cmd, reg + P_NAND_CMD);
}
-static void aml_cmd_n2m_page0(aml_raw_nand_t *raw_nand)
-{
+static void aml_cmd_n2m_page0(aml_raw_nand_t* raw_nand) {
uint32_t cmd;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
/*
@@ -197,16 +188,15 @@
* and rand-mode == 1.
*/
cmd = CMDRWGEN(AML_CMD_N2M,
- 1, /* force rand_mode */
- AML_ECC_BCH60_1K, /* force bch_mode */
- 1, /* shortm == 1 */
+ 1, /* force rand_mode */
+ AML_ECC_BCH60_1K, /* force bch_mode */
+ 1, /* shortm == 1 */
384 >> 3,
1);
writel(cmd, reg + P_NAND_CMD);
}
-static zx_status_t aml_wait_dma_finish(aml_raw_nand_t *raw_nand)
-{
+static zx_status_t aml_wait_dma_finish(aml_raw_nand_t* raw_nand) {
aml_cmd_idle(raw_nand, 0);
aml_cmd_idle(raw_nand, 0);
return aml_wait_cmd_finish(raw_nand, DMA_BUSY_TIMEOUT);
@@ -216,12 +206,11 @@
* Return the aml_info_format struct corresponding to the i'th
* ECC page. THIS ASSUMES user_mode == 2 (2 OOB bytes per ECC page).
*/
-static struct aml_info_format *aml_info_ptr(aml_raw_nand_t *raw_nand,
- int i)
-{
- struct aml_info_format *p;
+static struct aml_info_format* aml_info_ptr(aml_raw_nand_t* raw_nand,
+ int i) {
+ struct aml_info_format* p;
- p = (struct aml_info_format *)raw_nand->info_buf;
+ p = (struct aml_info_format*)raw_nand->info_buf;
return &p[i];
}
@@ -230,10 +219,9 @@
* struct per ECC page on completion of a read. This 8 byte structure has
* the 2 OOB bytes and ECC/error status
*/
-static zx_status_t aml_get_oob_byte(aml_raw_nand_t *raw_nand,
- uint8_t *oob_buf)
-{
- struct aml_info_format *info;
+static zx_status_t aml_get_oob_byte(aml_raw_nand_t* raw_nand,
+ uint8_t* oob_buf) {
+ struct aml_info_format* info;
int count = 0;
uint32_t ecc_pagesize, ecc_pages;
@@ -256,11 +244,10 @@
return ZX_OK;
}
-static zx_status_t aml_set_oob_byte(aml_raw_nand_t *raw_nand,
- uint8_t *oob_buf,
- uint32_t ecc_pages)
-{
- struct aml_info_format *info;
+static zx_status_t aml_set_oob_byte(aml_raw_nand_t* raw_nand,
+ uint8_t* oob_buf,
+ uint32_t ecc_pages) {
+ struct aml_info_format* info;
int count = 0;
/*
@@ -281,9 +268,8 @@
* Returns the maximum bitflips corrected on this NAND page
* (the maximum bitflips across all of the ECC pages in this page).
*/
-static int aml_get_ecc_corrections(aml_raw_nand_t *raw_nand, int ecc_pages)
-{
- struct aml_info_format *info;
+static int aml_get_ecc_corrections(aml_raw_nand_t* raw_nand, int ecc_pages) {
+ struct aml_info_format* info;
int bitflips = 0;
uint8_t zero_cnt;
@@ -315,9 +301,8 @@
return bitflips;
}
-static zx_status_t aml_check_ecc_pages(aml_raw_nand_t *raw_nand, int ecc_pages)
-{
- struct aml_info_format *info;
+static zx_status_t aml_check_ecc_pages(aml_raw_nand_t* raw_nand, int ecc_pages) {
+ struct aml_info_format* info;
for (int i = 0; i < ecc_pages; i++) {
info = aml_info_ptr(raw_nand, i);
@@ -327,11 +312,10 @@
return ZX_OK;
}
-static zx_status_t aml_queue_rb(aml_raw_nand_t *raw_nand)
-{
+static zx_status_t aml_queue_rb(aml_raw_nand_t* raw_nand) {
uint32_t cmd, cfg;
zx_status_t status;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
raw_nand->req_completion = COMPLETION_INIT;
@@ -354,12 +338,11 @@
return status;
}
-static void aml_cmd_ctrl(void *ctx,
- int32_t cmd, uint32_t ctrl)
-{
- aml_raw_nand_t *raw_nand = (aml_raw_nand_t *)ctx;
+static void aml_cmd_ctrl(void* ctx,
+ int32_t cmd, uint32_t ctrl) {
+ aml_raw_nand_t* raw_nand = (aml_raw_nand_t*)ctx;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
if (cmd == NAND_CMD_NONE)
@@ -372,11 +355,10 @@
}
/* Read status byte */
-static uint8_t aml_read_byte(void *ctx)
-{
- aml_raw_nand_t *raw_nand = (aml_raw_nand_t *)ctx;
+static uint8_t aml_read_byte(void* ctx) {
+ aml_raw_nand_t* raw_nand = (aml_raw_nand_t*)ctx;
uint32_t cmd;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
cmd = raw_nand->chip_select | AML_CMD_DRD | 0;
@@ -392,11 +374,10 @@
}
static void aml_set_clock_rate(aml_raw_nand_t* raw_nand,
- uint32_t clk_freq)
-{
+ uint32_t clk_freq) {
uint32_t always_on = 0x1 << 24;
uint32_t clk;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[CLOCKREG_WINDOW]);
/* For Amlogic type AXG */
@@ -422,23 +403,21 @@
writel(clk, reg);
}
-static void aml_clock_init(aml_raw_nand_t* raw_nand)
-{
+static void aml_clock_init(aml_raw_nand_t* raw_nand) {
uint32_t sys_clk_rate, bus_cycle, bus_timing;
sys_clk_rate = 200;
aml_set_clock_rate(raw_nand, sys_clk_rate);
- bus_cycle = 6;
+ bus_cycle = 6;
bus_timing = bus_cycle + 1;
nandctrl_set_cfg(raw_nand, 0);
nandctrl_set_timing_async(raw_nand, bus_timing, (bus_cycle - 1));
- nandctrl_send_cmd(raw_nand, 1<<31);
+ nandctrl_send_cmd(raw_nand, 1 << 31);
}
static void aml_adjust_timings(aml_raw_nand_t* raw_nand,
uint32_t tRC_min, uint32_t tREA_max,
- uint32_t RHOH_min)
-{
+ uint32_t RHOH_min) {
int sys_clk_rate, bus_cycle, bus_timing;
if (!tREA_max)
@@ -452,40 +431,38 @@
else
sys_clk_rate = 250;
aml_set_clock_rate(raw_nand, sys_clk_rate);
- bus_cycle = 6;
+ bus_cycle = 6;
bus_timing = bus_cycle + 1;
nandctrl_set_cfg(raw_nand, 0);
nandctrl_set_timing_async(raw_nand, bus_timing, (bus_cycle - 1));
- nandctrl_send_cmd(raw_nand, 1<<31);
+ nandctrl_send_cmd(raw_nand, 1 << 31);
}
-static bool is_page0_nand_page(uint32_t nand_page)
-{
+static bool is_page0_nand_page(uint32_t nand_page) {
return ((nand_page <= AML_PAGE0_MAX_ADDR) &&
((nand_page % AML_PAGE0_STEP) == 0));
}
-static zx_status_t aml_read_page_hwecc(void *ctx,
- void *data,
- void *oob,
+static zx_status_t aml_read_page_hwecc(void* ctx,
+ void* data,
+ void* oob,
uint32_t nand_page,
- int *ecc_correct)
-{
- aml_raw_nand_t *raw_nand = (aml_raw_nand_t *)ctx;
+ int* ecc_correct) {
+ aml_raw_nand_t* raw_nand = (aml_raw_nand_t*)ctx;
uint32_t cmd;
zx_status_t status;
uint64_t daddr = raw_nand->data_buf_paddr;
uint64_t iaddr = raw_nand->info_buf_paddr;
int ecc_c;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
- uint32_t ecc_pagesize = 0; /* initialize to silence compiler */
+ uint32_t ecc_pagesize = 0; /* initialize to silence compiler */
uint32_t ecc_pages;
bool page0 = is_page0_nand_page(nand_page);
if (!page0) {
ecc_pagesize = aml_get_ecc_pagesize(raw_nand,
- raw_nand->controller_params.bch_mode );
+ raw_nand->controller_params.bch_mode);
ecc_pages = raw_nand->writesize / ecc_pagesize;
if (is_page0_nand_page(nand_page))
return ZX_ERR_IO;
@@ -498,7 +475,7 @@
io_buffer_cache_flush_invalidate(&raw_nand->data_buffer, 0,
raw_nand->writesize);
io_buffer_cache_flush_invalidate(&raw_nand->info_buffer, 0,
- ecc_pages * sizeof(struct aml_info_format));
+ ecc_pages * sizeof(struct aml_info_format));
/* Send the page address into the controller */
onfi_command(&raw_nand->raw_nand_proto, NAND_CMD_READ0, 0x00,
nand_page, raw_nand->chipsize, raw_nand->controller_delay,
@@ -517,7 +494,7 @@
* Only need to set the seed if randomizing
* is enabled.
*/
- aml_cmd_seed(raw_nand, nand_page);
+ aml_cmd_seed(raw_nand, nand_page);
if (!page0)
aml_cmd_n2m(raw_nand, ecc_pages, ecc_pagesize);
else
@@ -548,9 +525,9 @@
status = aml_get_oob_byte(raw_nand, oob);
ecc_c = aml_get_ecc_corrections(raw_nand, ecc_pages);
if (ecc_c < 0) {
- zxlogf(ERROR, "%s: Uncorrectable ECC error on read\n",
- __func__);
- status = ZX_ERR_IO;
+ zxlogf(ERROR, "%s: Uncorrectable ECC error on read\n",
+ __func__);
+ status = ZX_ERR_IO;
}
*ecc_correct = ecc_c;
return status;
@@ -560,19 +537,18 @@
* TODO : Right now, the driver uses a buffer for DMA, which
* is not needed. We should initiate DMA to/from pages passed in.
*/
-static zx_status_t aml_write_page_hwecc(void *ctx,
- void *data,
- void *oob,
- uint32_t nand_page)
-{
- aml_raw_nand_t *raw_nand = (aml_raw_nand_t *)ctx;
+static zx_status_t aml_write_page_hwecc(void* ctx,
+ void* data,
+ void* oob,
+ uint32_t nand_page) {
+ aml_raw_nand_t* raw_nand = (aml_raw_nand_t*)ctx;
uint32_t cmd;
uint64_t daddr = raw_nand->data_buf_paddr;
uint64_t iaddr = raw_nand->info_buf_paddr;
zx_status_t status;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
- uint32_t ecc_pagesize = 0; /* initialize to silence compiler */
+ uint32_t ecc_pagesize = 0; /* initialize to silence compiler */
uint32_t ecc_pages;
bool page0 = is_page0_nand_page(nand_page);
@@ -592,7 +568,7 @@
if (oob != NULL) {
aml_set_oob_byte(raw_nand, oob, ecc_pages);
io_buffer_cache_flush_invalidate(&raw_nand->info_buffer, 0,
- ecc_pages * sizeof(struct aml_info_format));
+ ecc_pages * sizeof(struct aml_info_format));
}
onfi_command(&raw_nand->raw_nand_proto, NAND_CMD_SEQIN, 0x00, nand_page,
@@ -612,7 +588,7 @@
* Only need to set the seed if randomizing
* is enabled.
*/
- aml_cmd_seed(raw_nand, nand_page);
+ aml_cmd_seed(raw_nand, nand_page);
if (!page0)
aml_cmd_m2n(raw_nand, ecc_pages, ecc_pagesize);
else
@@ -635,9 +611,8 @@
* Erase entry point into the Amlogic driver.
* nandblock : NAND erase block address.
*/
-static zx_status_t aml_erase_block(void *ctx, uint32_t nand_page)
-{
- aml_raw_nand_t *raw_nand = (aml_raw_nand_t *)ctx;
+static zx_status_t aml_erase_block(void* ctx, uint32_t nand_page) {
+ aml_raw_nand_t* raw_nand = (aml_raw_nand_t*)ctx;
zx_status_t status;
/* nandblock has to be erasesize aligned */
@@ -656,13 +631,12 @@
return status;
}
-static zx_status_t aml_get_flash_type(aml_raw_nand_t *raw_nand)
-{
+static zx_status_t aml_get_flash_type(aml_raw_nand_t* raw_nand) {
uint8_t nand_maf_id, nand_dev_id;
uint8_t id_data[8];
- struct nand_chip_table *nand_chip;
+ struct nand_chip_table* nand_chip;
- onfi_command(&raw_nand->raw_nand_proto, NAND_CMD_RESET, -1, -1,
+ onfi_command(&raw_nand->raw_nand_proto, NAND_CMD_RESET, -1, -1,
raw_nand->chipsize, raw_nand->controller_delay,
(raw_nand->controller_params.options & NAND_BUSWIDTH_16));
onfi_command(&raw_nand->raw_nand_proto, NAND_CMD_READID, 0x00, -1,
@@ -689,37 +663,37 @@
nand_chip = find_nand_chip_table(nand_maf_id, nand_dev_id);
if (nand_chip == NULL) {
zxlogf(ERROR, "%s: Cound not find matching NAND chip. NAND chip unsupported."
- " This is FATAL\n",
+ " This is FATAL\n",
__func__);
return ZX_ERR_UNAVAILABLE;
}
if (nand_chip->extended_id_nand) {
- /*
+ /*
* Initialize pagesize, eraseblk size, oobsize and
* buswidth from extended parameters queried just now.
*/
- uint8_t extid = id_data[3];
+ uint8_t extid = id_data[3];
- raw_nand->writesize = 1024 << (extid & 0x03);
- extid >>= 2;
- /* Calc oobsize */
- raw_nand->oobsize = (8 << (extid & 0x01)) *
- (raw_nand->writesize >> 9);
- extid >>= 2;
- /* Calc blocksize. Blocksize is multiples of 64KiB */
- raw_nand->erasesize = (64 * 1024) << (extid & 0x03);
- extid >>= 2;
- /* Get buswidth information */
- raw_nand->bus_width = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
+ raw_nand->writesize = 1024 << (extid & 0x03);
+ extid >>= 2;
+ /* Calc oobsize */
+ raw_nand->oobsize = (8 << (extid & 0x01)) *
+ (raw_nand->writesize >> 9);
+ extid >>= 2;
+ /* Calc blocksize. Blocksize is multiples of 64KiB */
+ raw_nand->erasesize = (64 * 1024) << (extid & 0x03);
+ extid >>= 2;
+ /* Get buswidth information */
+ raw_nand->bus_width = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
} else {
- /*
+ /*
* Initialize pagesize, eraseblk size, oobsize and
* buswidth from values in table.
*/
- raw_nand->writesize = nand_chip->page_size;
- raw_nand->oobsize = nand_chip->oobsize;
- raw_nand->erasesize = nand_chip->erase_block_size;
- raw_nand->bus_width = nand_chip->bus_width;
+ raw_nand->writesize = nand_chip->page_size;
+ raw_nand->oobsize = nand_chip->oobsize;
+ raw_nand->erasesize = nand_chip->erase_block_size;
+ raw_nand->bus_width = nand_chip->bus_width;
}
raw_nand->erasesize_pages =
raw_nand->erasesize / raw_nand->writesize;
@@ -738,7 +712,7 @@
return ZX_OK;
}
-static int aml_raw_nand_irq_thread(void *arg) {
+static int aml_raw_nand_irq_thread(void* arg) {
zxlogf(INFO, "aml_raw_nand_irq_thread start\n");
aml_raw_nand_t* raw_nand = arg;
@@ -763,9 +737,8 @@
return 0;
}
-static zx_status_t aml_get_nand_info(void *ctx, struct nand_info *nand_info)
-{
- aml_raw_nand_t *raw_nand = (aml_raw_nand_t *)ctx;
+static zx_status_t aml_get_nand_info(void* ctx, struct nand_info* nand_info) {
+ aml_raw_nand_t* raw_nand = (aml_raw_nand_t*)ctx;
uint64_t capacity;
zx_status_t status = ZX_OK;
@@ -782,7 +755,8 @@
if (raw_nand->controller_params.user_mode == 2)
nand_info->oob_size =
(raw_nand->writesize /
- aml_get_ecc_pagesize(raw_nand, raw_nand->controller_params.bch_mode)) * 2;
+ aml_get_ecc_pagesize(raw_nand, raw_nand->controller_params.bch_mode)) *
+ 2;
else
status = ZX_ERR_NOT_SUPPORTED;
return status;
@@ -800,8 +774,8 @@
static void aml_raw_nand_release(void* ctx) {
aml_raw_nand_t* raw_nand = ctx;
- for (raw_nand_addr_window_t wnd = 0 ;
- wnd < ADDR_WINDOW_COUNT ;
+ for (raw_nand_addr_window_t wnd = 0;
+ wnd < ADDR_WINDOW_COUNT;
wnd++)
io_buffer_release(&raw_nand->mmio[wnd]);
io_buffer_release(&raw_nand->data_buffer);
@@ -810,10 +784,9 @@
free(raw_nand);
}
-static void aml_set_encryption(aml_raw_nand_t *raw_nand)
-{
+static void aml_set_encryption(aml_raw_nand_t* raw_nand) {
uint32_t cfg;
- volatile uint8_t *reg = (volatile uint8_t*)
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
cfg = readl(reg + P_NAND_CFG);
@@ -822,12 +795,11 @@
}
static zx_status_t aml_read_page0(aml_raw_nand_t* raw_nand,
- void *data,
- void *oob,
+ void* data,
+ void* oob,
uint32_t nand_page,
- int *ecc_correct,
- int retries)
-{
+ int* ecc_correct,
+ int retries) {
zx_status_t status;
retries++;
@@ -844,11 +816,10 @@
* Read one of the page0 pages, and use the result to init
* ECC algorithm and rand-mode.
*/
-static zx_status_t aml_nand_init_from_page0(aml_raw_nand_t* raw_nand)
-{
+static zx_status_t aml_nand_init_from_page0(aml_raw_nand_t* raw_nand) {
zx_status_t status;
- char *data;
- nand_page0_t *page0;
+ char* data;
+ nand_page0_t* page0;
int ecc_correct;
data = malloc(raw_nand->writesize);
@@ -860,7 +831,7 @@
* There are 8 copies of page0 spaced apart by 128 pages
* starting at Page 0. Read the first we can.
*/
- for (uint32_t i = 0 ; i < 7 ; i++) {
+ for (uint32_t i = 0; i < 7; i++) {
status = aml_read_page0(raw_nand, data, NULL, i * 128,
&ecc_correct, 3);
if (status == ZX_OK)
@@ -876,7 +847,7 @@
return status;
}
- page0 = (nand_page0_t *)data;
+ page0 = (nand_page0_t*)data;
raw_nand->controller_params.rand_mode =
(page0->nand_setup.cfg.d32 >> 19) & 0x1;
raw_nand->controller_params.bch_mode =
@@ -887,14 +858,13 @@
return ZX_OK;
}
-static zx_status_t aml_raw_nand_allocbufs(aml_raw_nand_t* raw_nand)
-{
+static zx_status_t aml_raw_nand_allocbufs(aml_raw_nand_t* raw_nand) {
zx_status_t status;
status = pdev_get_bti(&raw_nand->pdev, 0, &raw_nand->bti_handle);
if (status != ZX_OK) {
zxlogf(ERROR, "raw_nand_test_allocbufs: pdev_get_bti failed (%d)\n",
- status);
+ status);
return status;
}
status = io_buffer_init(&raw_nand->data_buffer,
@@ -926,8 +896,7 @@
return ZX_OK;
}
-static zx_status_t aml_nand_init(aml_raw_nand_t* raw_nand)
-{
+static zx_status_t aml_nand_init(aml_raw_nand_t* raw_nand) {
zx_status_t status;
/*
@@ -990,8 +959,7 @@
.release = aml_raw_nand_release,
};
-static zx_status_t aml_raw_nand_bind(void* ctx, zx_device_t* parent)
-{
+static zx_status_t aml_raw_nand_bind(void* ctx, zx_device_t* parent) {
zx_status_t status;
aml_raw_nand_t* raw_nand = calloc(1, sizeof(aml_raw_nand_t));
@@ -1103,8 +1071,8 @@
return status;
fail:
- for (raw_nand_addr_window_t wnd = 0 ;
- wnd < ADDR_WINDOW_COUNT ;
+ for (raw_nand_addr_window_t wnd = 0;
+ wnd < ADDR_WINDOW_COUNT;
wnd++)
io_buffer_release(&raw_nand->mmio[wnd]);
free(raw_nand);
@@ -1117,7 +1085,7 @@
};
ZIRCON_DRIVER_BEGIN(aml_raw_nand, aml_raw_nand_driver_ops, "zircon", "0.1", 3)
- BI_ABORT_IF(NE, BIND_PROTOCOL, ZX_PROTOCOL_PLATFORM_DEV),
+BI_ABORT_IF(NE, BIND_PROTOCOL, ZX_PROTOCOL_PLATFORM_DEV),
BI_ABORT_IF(NE, BIND_PLATFORM_DEV_VID, PDEV_VID_AMLOGIC),
BI_MATCH_IF(EQ, BIND_PLATFORM_DEV_DID, PDEV_DID_AMLOGIC_RAW_NAND),
-ZIRCON_DRIVER_END(aml_raw_nand)
+ ZIRCON_DRIVER_END(aml_raw_nand)
diff --git a/system/dev/rawnand/aml-rawnand/aml-rawnand.h b/system/dev/rawnand/aml-rawnand/aml-rawnand.h
index a4982a1..8e7668a 100644
--- a/system/dev/rawnand/aml-rawnand/aml-rawnand.h
+++ b/system/dev/rawnand/aml-rawnand/aml-rawnand.h
@@ -7,14 +7,14 @@
typedef enum raw_nand_addr_window {
NANDREG_WINDOW = 0,
CLOCKREG_WINDOW,
- ADDR_WINDOW_COUNT, // always last
+ ADDR_WINDOW_COUNT, // always last
} raw_nand_addr_window_t;
typedef struct {
int ecc_strength;
int user_mode;
int rand_mode;
-#define NAND_USE_BOUNCE_BUFFER 0x1
+#define NAND_USE_BOUNCE_BUFFER 0x1
int options;
int bch_mode;
} aml_controller_t;
@@ -27,16 +27,16 @@
thrd_t irq_thread;
zx_handle_t irq_handle;
bool enabled;
- aml_controller_t controller_params;
+ aml_controller_t controller_params;
uint32_t chip_select;
int controller_delay;
- uint32_t writesize; /* NAND pagesize - bytes */
- uint32_t erasesize; /* size of erase block - bytes */
+ uint32_t writesize; /* NAND pagesize - bytes */
+ uint32_t erasesize; /* size of erase block - bytes */
uint32_t erasesize_pages;
- uint32_t oobsize; /* oob bytes per NAND page - bytes */
-#define NAND_BUSWIDTH_16 0x00000002
- uint32_t bus_width; /* 16bit or 8bit ? */
- uint64_t chipsize; /* MiB */
+ uint32_t oobsize; /* oob bytes per NAND page - bytes */
+#define NAND_BUSWIDTH_16 0x00000002
+ uint32_t bus_width; /* 16bit or 8bit ? */
+ uint64_t chipsize; /* MiB */
uint32_t page_shift; /* NAND page shift */
completion_t req_completion;
struct {
@@ -50,38 +50,33 @@
zx_paddr_t info_buf_paddr, data_buf_paddr;
} aml_raw_nand_t;
-static inline void set_bits(uint32_t *_reg, const uint32_t _value,
- const uint32_t _start, const uint32_t _len)
-{
- writel(((readl(_reg) & ~(((1L << (_len))-1) << (_start)))
- | ((uint32_t)((_value)&((1L<<(_len))-1)) << (_start))), _reg);
+static inline void set_bits(uint32_t* _reg, const uint32_t _value,
+ const uint32_t _start, const uint32_t _len) {
+ writel(((readl(_reg) & ~(((1L << (_len)) - 1) << (_start))) | ((uint32_t)((_value) & ((1L << (_len)) - 1)) << (_start))), _reg);
}
-static inline void nandctrl_set_cfg(aml_raw_nand_t *raw_nand,
- uint32_t val)
-{
- volatile uint8_t *reg = (volatile uint8_t*)
+static inline void nandctrl_set_cfg(aml_raw_nand_t* raw_nand,
+ uint32_t val) {
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
writel(val, reg + P_NAND_CFG);
}
-static inline void nandctrl_set_timing_async(aml_raw_nand_t *raw_nand,
+static inline void nandctrl_set_timing_async(aml_raw_nand_t* raw_nand,
int bus_tim,
- int bus_cyc)
-{
- volatile uint8_t *reg = (volatile uint8_t*)
+ int bus_cyc) {
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
- set_bits((uint32_t *)(reg + P_NAND_CFG),
- ((bus_cyc&31)|((bus_tim&31)<<5)|(0<<10)),
+ set_bits((uint32_t*)(reg + P_NAND_CFG),
+ ((bus_cyc & 31) | ((bus_tim & 31) << 5) | (0 << 10)),
0, 12);
}
-static inline void nandctrl_send_cmd(aml_raw_nand_t *raw_nand,
- uint32_t cmd)
-{
- volatile uint8_t *reg = (volatile uint8_t*)
+static inline void nandctrl_send_cmd(aml_raw_nand_t* raw_nand,
+ uint32_t cmd) {
+ volatile uint8_t* reg = (volatile uint8_t*)
io_buffer_virt(&raw_nand->mmio[NANDREG_WINDOW]);
writel(cmd, reg + P_NAND_CMD);
@@ -91,10 +86,10 @@
* Controller ECC, OOB, RAND parameters
*/
struct aml_controller_params {
- int ecc_strength; /* # of ECC bits per ECC page */
- int user_mode; /* OOB bytes every ECC page or per block ? */
- int rand_mode; /* Randomize ? */
- int bch_mode;
+ int ecc_strength; /* # of ECC bits per ECC page */
+ int user_mode; /* OOB bytes every ECC page or per block ? */
+ int rand_mode; /* Randomize ? */
+ int bch_mode;
};
/*
@@ -104,7 +99,7 @@
*/
struct __attribute__((packed)) aml_info_format {
uint16_t info_bytes;
- uint8_t zero_cnt; /* bit0~5 is valid */
+ uint8_t zero_cnt; /* bit0~5 is valid */
struct ecc_sta {
uint8_t eccerr_cnt : 6;
uint8_t notused : 1;
@@ -118,18 +113,18 @@
typedef struct nand_setup {
union {
- uint32_t d32;
- struct {
- unsigned cmd:22;
- unsigned large_page:1;
- unsigned no_rb:1;
- unsigned a2:1;
- unsigned reserved25:1;
- unsigned page_list:1;
- unsigned sync_mode:2;
- unsigned size:2;
- unsigned active:1;
- } b;
+ uint32_t d32;
+ struct {
+ unsigned cmd : 22;
+ unsigned large_page : 1;
+ unsigned no_rb : 1;
+ unsigned a2 : 1;
+ unsigned reserved25 : 1;
+ unsigned page_list : 1;
+ unsigned sync_mode : 2;
+ unsigned size : 2;
+ unsigned active : 1;
+ } b;
} cfg;
uint16_t id;
uint16_t max;
@@ -140,7 +135,6 @@
uint8_t val;
} nand_cmd_t;
-
typedef struct _ext_info {
uint32_t read_info;
uint32_t new_type;
@@ -160,15 +154,15 @@
ext_info_t ext_info;
} nand_page0_t;
-#define AML_PAGE0_LEN 384
+#define AML_PAGE0_LEN 384
/*
* Backup copies of page0 are located every 128 pages,
* with the last one at 896.
*/
-#define AML_PAGE0_STEP 128
-#define AML_PAGE0_MAX_ADDR 896
+#define AML_PAGE0_STEP 128
+#define AML_PAGE0_MAX_ADDR 896
/*
* NAND timing defaults
*/
-#define TREA_MAX_DEFAULT 20
-#define RHOH_MIN_DEFAULT 15
+#define TREA_MAX_DEFAULT 20
+#define RHOH_MIN_DEFAULT 15
diff --git a/system/dev/rawnand/aml-rawnand/onfi.c b/system/dev/rawnand/aml-rawnand/onfi.c
index fdaf1b9..78d5b3b 100644
--- a/system/dev/rawnand/aml-rawnand/onfi.c
+++ b/system/dev/rawnand/aml-rawnand/onfi.c
@@ -10,37 +10,34 @@
#include <ddk/debug.h>
#include <ddk/protocol/rawnand.h>
+#include <sync/completion.h>
#include <zircon/assert.h>
+#include <zircon/status.h>
#include <zircon/threads.h>
#include <zircon/types.h>
-#include <zircon/status.h>
-#include <sync/completion.h>
-#include <string.h>
#include "onfi.h"
+#include <string.h>
/*
* Database of settings for the NAND flash devices we support
*/
struct nand_chip_table nand_chip_table[] = {
- { 0xEC, 0xDC, "Samsung", "K9F4G08U0F", { 25, 20, 15 }, true, 512,
- 0, 0, 0, 0 },
+ {0xEC, 0xDC, "Samsung", "K9F4G08U0F", {25, 20, 15}, true, 512, 0, 0, 0, 0},
/* TODO: This works. but doublecheck Toshiba nand_timings from datasheet */
- { 0x98, 0xDC, "Toshiba", "TC58NVG2S0F", { 25, 20, /* 15 */ 25 }, true, 512,
- 0, 0, 0, 0 },
+ {0x98, 0xDC, "Toshiba", "TC58NVG2S0F", {25, 20, /* 15 */ 25}, true, 512, 0, 0, 0, 0},
};
-#define NAND_CHIP_TABLE_SIZE \
- (sizeof(nand_chip_table)/sizeof(struct nand_chip_table))
+#define NAND_CHIP_TABLE_SIZE \
+ (sizeof(nand_chip_table) / sizeof(struct nand_chip_table))
/*
* Find the entry in the NAND chip table database based on manufacturer
* id and device id
*/
-struct nand_chip_table *find_nand_chip_table(uint8_t manuf_id,
- uint8_t device_id)
-{
- for (uint32_t i = 0 ; i < NAND_CHIP_TABLE_SIZE ; i++)
+struct nand_chip_table* find_nand_chip_table(uint8_t manuf_id,
+ uint8_t device_id) {
+ for (uint32_t i = 0; i < NAND_CHIP_TABLE_SIZE; i++)
if (manuf_id == nand_chip_table[i].manufacturer_id &&
device_id == nand_chip_table[i].device_id)
return &nand_chip_table[i];
@@ -53,20 +50,19 @@
* Generic wait function used by both program (write) and erase
* functionality.
*/
-zx_status_t onfi_wait(raw_nand_protocol_t *proto, uint32_t timeout_ms)
-{
+zx_status_t onfi_wait(raw_nand_protocol_t* proto, uint32_t timeout_ms) {
uint64_t total_time = 0;
uint8_t cmd_status;
raw_nand_cmd_ctrl(proto, NAND_CMD_STATUS,
- NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ NAND_CTRL_CLE | NAND_CTRL_CHANGE);
raw_nand_cmd_ctrl(proto, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
while (!((cmd_status = raw_nand_read_byte(proto)) & NAND_STATUS_READY)) {
- usleep(10);
- total_time += 10;
- if (total_time > (timeout_ms * 1000)) {
- break;
- }
+ usleep(10);
+ total_time += 10;
+ if (total_time > (timeout_ms * 1000)) {
+ break;
+ }
}
if (!(cmd_status & NAND_STATUS_READY)) {
zxlogf(ERROR, "nand command wait timed out\n");
@@ -82,11 +78,10 @@
/*
* Send onfi command down to the controller.
*/
-void onfi_command(raw_nand_protocol_t *proto, uint32_t command,
+void onfi_command(raw_nand_protocol_t* proto, uint32_t command,
int32_t column, int32_t page_addr,
uint32_t capacity_mb, uint32_t controller_delay_us,
- int buswidth_16)
-{
+ int buswidth_16) {
raw_nand_cmd_ctrl(proto, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
if (column != -1 || page_addr != -1) {
uint32_t ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
@@ -102,11 +97,11 @@
if (page_addr != -1) {
raw_nand_cmd_ctrl(proto, page_addr, ctrl);
raw_nand_cmd_ctrl(proto, page_addr >> 8,
- NAND_NCE | NAND_ALE);
+ NAND_NCE | NAND_ALE);
/* one more address cycle for devices > 128M */
if (capacity_mb > 128)
raw_nand_cmd_ctrl(proto, page_addr >> 16,
- NAND_NCE | NAND_ALE);
+ NAND_NCE | NAND_ALE);
}
}
raw_nand_cmd_ctrl(proto, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
@@ -117,9 +112,9 @@
if (command == NAND_CMD_RESET) {
usleep(controller_delay_us);
raw_nand_cmd_ctrl(proto, NAND_CMD_STATUS,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
raw_nand_cmd_ctrl(proto, NAND_CMD_NONE,
- NAND_NCE | NAND_CTRL_CHANGE);
+ NAND_NCE | NAND_CTRL_CHANGE);
/* We have to busy loop until ready */
while (!(raw_nand_read_byte(proto) & NAND_STATUS_READY))
;
@@ -127,11 +122,9 @@
}
if (command == NAND_CMD_READ0) {
raw_nand_cmd_ctrl(proto, NAND_CMD_READSTART,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
raw_nand_cmd_ctrl(proto, NAND_CMD_NONE,
- NAND_NCE | NAND_CTRL_CHANGE);
+ NAND_NCE | NAND_CTRL_CHANGE);
}
usleep(controller_delay_us);
}
-
-
diff --git a/system/dev/rawnand/aml-rawnand/onfi.h b/system/dev/rawnand/aml-rawnand/onfi.h
index 4fe616d..0a9de8f 100644
--- a/system/dev/rawnand/aml-rawnand/onfi.h
+++ b/system/dev/rawnand/aml-rawnand/onfi.h
@@ -4,38 +4,38 @@
#pragma once
-#define NAND_CE0 (0xe<<10)
-#define NAND_CE1 (0xd<<10)
+#define NAND_CE0 (0xe << 10)
+#define NAND_CE1 (0xd << 10)
-#define NAND_NCE 0x01
-#define NAND_CLE 0x02
-#define NAND_ALE 0x04
+#define NAND_NCE 0x01
+#define NAND_CLE 0x02
+#define NAND_ALE 0x04
-#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
-#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
-#define NAND_CTRL_CHANGE 0x80
+#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
+#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
+#define NAND_CTRL_CHANGE 0x80
-#define NAND_CMD_READ0 0
-#define NAND_CMD_READ1 1
-#define NAND_CMD_PAGEPROG 0x10
-#define NAND_CMD_READOOB 0x50
-#define NAND_CMD_ERASE1 0x60
-#define NAND_CMD_STATUS 0x70
-#define NAND_CMD_SEQIN 0x80
-#define NAND_CMD_READID 0x90
-#define NAND_CMD_ERASE2 0xd0
-#define NAND_CMD_RESET 0xff
-#define NAND_CMD_NONE -1
+#define NAND_CMD_READ0 0
+#define NAND_CMD_READ1 1
+#define NAND_CMD_PAGEPROG 0x10
+#define NAND_CMD_READOOB 0x50
+#define NAND_CMD_ERASE1 0x60
+#define NAND_CMD_STATUS 0x70
+#define NAND_CMD_SEQIN 0x80
+#define NAND_CMD_READID 0x90
+#define NAND_CMD_ERASE2 0xd0
+#define NAND_CMD_RESET 0xff
+#define NAND_CMD_NONE -1
/* Extended commands for large page devices */
-#define NAND_CMD_READSTART 0x30
+#define NAND_CMD_READSTART 0x30
/* Status */
-#define NAND_STATUS_FAIL 0x01
-#define NAND_STATUS_FAIL_N1 0x02
-#define NAND_STATUS_TRUE_READY 0x20
-#define NAND_STATUS_READY 0x40
-#define NAND_STATUS_WP 0x80
+#define NAND_STATUS_FAIL 0x01
+#define NAND_STATUS_FAIL_N1 0x02
+#define NAND_STATUS_TRUE_READY 0x20
+#define NAND_STATUS_READY 0x40
+#define NAND_STATUS_WP 0x80
struct nand_timings {
uint32_t tRC_min;
@@ -44,33 +44,31 @@
};
struct nand_chip_table {
- uint8_t manufacturer_id;
- uint8_t device_id;
- const char *manufacturer_name;
- const char *device_name;
+ uint8_t manufacturer_id;
+ uint8_t device_id;
+ const char* manufacturer_name;
+ const char* device_name;
struct nand_timings timings;
/*
* extended_id_nand -> pagesize, erase blocksize, OOB size
* could vary given the same device id.
*/
- bool extended_id_nand;
- uint64_t chipsize; /* MiB */
+ bool extended_id_nand;
+ uint64_t chipsize; /* MiB */
/* Valid only if extended_id_nand is false */
- uint32_t page_size; /* bytes */
- uint32_t oobsize; /* bytes */
- uint32_t erase_block_size; /* bytes */
- uint32_t bus_width; /* 8 vs 16 bit */
+ uint32_t page_size; /* bytes */
+ uint32_t oobsize; /* bytes */
+ uint32_t erase_block_size; /* bytes */
+ uint32_t bus_width; /* 8 vs 16 bit */
};
-#define MAX(A, B) ((A > B) ? A : B)
-#define MIN(A, B) ((A < B) ? A : B)
+#define MAX(A, B) ((A > B) ? A : B)
+#define MIN(A, B) ((A < B) ? A : B)
-struct nand_chip_table *find_nand_chip_table(uint8_t manuf_id,
+struct nand_chip_table* find_nand_chip_table(uint8_t manuf_id,
uint8_t device_id);
-void onfi_command(raw_nand_protocol_t *proto, uint32_t command,
+void onfi_command(raw_nand_protocol_t* proto, uint32_t command,
int32_t column, int32_t page_addr,
uint32_t capacity_mb, uint32_t controller_delay_us,
int buswidth_16);
-zx_status_t onfi_wait(raw_nand_protocol_t *proto, uint32_t timeout_ms);
-
-
+zx_status_t onfi_wait(raw_nand_protocol_t* proto, uint32_t timeout_ms);
