| // Copyright 2017 The Fuchsia Authors. All rights reserved. |
| // Use of this source code is governed by a BSD-style license that can be |
| // found in the LICENSE file. |
| |
| // Table of categories for configuring Intel Performance Monitor hardware. |
| // TODO(dje): For now assume skylake/kabylake. |
| |
| #ifndef DEF_CATEGORY |
| #error "DEF_CATEGORY not defined" |
| #endif |
| |
| // Arguments: |
| // - symbol |
| // - id (must be within IPM_CATEGORY_PROGRAMMABLE_MASK) |
| // - name (cannot have any spaces, used in trace category name) |
| // - varargs list of register names |
| |
| DEF_CATEGORY(IPM_CATEGORY_NONE, 0, "") |
| |
| DEF_CATEGORY(IPM_CATEGORY_ARCH_LLC, 1, "arch_llc", |
| ARCH_LLC_REFERENCE, |
| ARCH_LLC_MISSES) |
| |
| DEF_CATEGORY(IPM_CATEGORY_ARCH_BRANCH, 2, "arch_branch", |
| ARCH_BRANCH_INSTRUCTIONS_RETIRED, |
| ARCH_BRANCH_MISSES_RETIRED) |
| |
| DEF_CATEGORY(IPM_CATEGORY_DTLB_LOAD, 10, "dtlb_load", |
| SKL_DTLB_LOAD_MISSES_MISS_CAUSES_A_WALK, |
| SKL_DTLB_LOAD_MISSES_WALK_COMPLETED, |
| SKL_DTLB_LOAD_MISSES_WALK_PENDING, |
| SKL_DTLB_LOAD_MISSES_WALK_ACTIVE, |
| SKL_DTLB_LOAD_MISSES_STLB_HIT) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L2_DATA, 11, "l2_data", |
| SKL_L2_RQSTS_DEMAND_DATA_RD_MISS, |
| SKL_L2_RQSTS_DEMAND_DATA_RD_HIT, |
| SKL_L2_RQSTS_ALL_DEMAND_DATA_RD) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L2_CODE, 12, "l2_code", |
| SKL_L2_RQSTS_CODE_RD_MISS, |
| SKL_L2_RQSTS_CODE_RD_HIT, |
| SKL_L2_RQSTS_ALL_CODE_RD) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L2_RFO, 13, "l2_rfo", |
| SKL_L2_RQSTS_RFO_MISS, |
| SKL_L2_RQSTS_RFO_HIT, |
| SKL_L2_RQSTS_ALL_RFO) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L2_ALL, 14, "l2_summary", |
| SKL_L2_RQSTS_ALL_DEMAND_MISS, |
| SKL_L2_RQSTS_MISS, |
| SKL_L2_RQSTS_PF_HIT, |
| SKL_L2_RQSTS_ALL_DEMAND_REFERENCES, |
| SKL_L2_RQSTS_REFERENCES) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L3_SUMMARY, 15, "l3_summary", |
| SKL_LONGEST_LAT_CACHE_REFERENCE, |
| SKL_LONGEST_LAT_CACHE_MISS) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L1_SUMMARY, 16, "l1_summary", |
| SKL_L1D_PEND_MISS_PENDING_CYCLES, |
| SKL_L1D_PEND_MISS_PENDING_CYCLES_ANY, |
| SKL_L1D_REPLACEMENT) |
| |
| DEF_CATEGORY(IPM_CATEGORY_DTLB_STORE, 17, "dtlb_store", |
| SKL_DTLB_STORE_MISSES_MISS_CAUSES_A_WALK, |
| SKL_DTLB_STORE_MISSES_WALK_COMPLETED, |
| SKL_DTLB_STORE_MISSES_WALK_PENDING, |
| SKL_DTLB_STORE_MISSES_WALK_ACTIVE, |
| SKL_DTLB_STORE_MISSES_STLB_HIT) |
| |
| DEF_CATEGORY(IPM_CATEGORY_OFFCORE_DEMAND_DATA, 18, "offcore_demand_data", |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD, |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD, |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD_GE_6) |
| |
| DEF_CATEGORY(IPM_CATEGORY_OFFCORE_CODE, 19, "offcore_code", |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_CODE_RD, |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD) |
| |
| DEF_CATEGORY(IPM_CATEGORY_OFFCORE_RFO, 20, "offcore_rfo", |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_RFO, |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO) |
| |
| DEF_CATEGORY(IPM_CATEGORY_OFFCORE_DATA, 21, "offcore_data", |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_DATA_RD, |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD) |
| |
| DEF_CATEGORY(IPM_CATEGORY_OFFCORE_L3_MISS, 22, "offcore_l3_miss", |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD, |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD, |
| SKL_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD_GE_6) |
| |
| DEF_CATEGORY(IPM_CATEGORY_ICACHE, 23, "icache", |
| SKL_ICACHE_64B_IFDATA_STALL, |
| SKL_ICACHE_64B_IFTAG_HIT, |
| SKL_ICACHE_64B_IFTAG_MISS) |
| |
| DEF_CATEGORY(IPM_CATEGORY_ITLB, 24, "itlb", |
| SKL_ITLB_MISSES_MISS_CAUSES_A_WALK, |
| SKL_ITLB_MISSES_WALK_COMPLETED, |
| SKL_ITLB_MISSES_WALK_PENDING, |
| SKL_ITLB_MISSES_STLB_HIT) |
| |
| DEF_CATEGORY(IPM_CATEGORY_STALL_SUMMARY, 25, "stall_summary", |
| SKL_RESOURCE_STALLS_ANY, |
| SKL_RESOURCE_STALLS_SB) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L1_CYCLES, 26, "l1_miss_cycles", |
| SKL_CYCLE_ACTIVITY_CYCLES_L1D_MISS, |
| SKL_CYCLE_ACTIVITY_STALLS_L1D_MISS) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L2_CYCLES, 27, "l2_miss_cycles", |
| SKL_CYCLE_ACTIVITY_CYCLES_L2_MISS, |
| SKL_CYCLE_ACTIVITY_STALLS_L2_MISS) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L3_CYCLES, 28, "l3_miss_cycles", |
| SKL_CYCLE_ACTIVITY_CYCLES_L3_MISS, |
| SKL_CYCLE_ACTIVITY_STALLS_L3_MISS) |
| |
| DEF_CATEGORY(IPM_CATEGORY_MEM_CYCLES, 29, "mem_cycles", |
| SKL_CYCLE_ACTIVITY_CYCLES_MEM_ANY, |
| SKL_CYCLE_ACTIVITY_STALLS_MEM_ANY) |
| |
| DEF_CATEGORY(IPM_CATEGORY_OFFCORE_REQUESTS, 30, "offcore_requests", |
| SKL_OFFCORE_REQUESTS_DEMAND_DATA_RD, |
| SKL_OFFCORE_REQUESTS_DEMAND_CODE_RD, |
| SKL_OFFCORE_REQUESTS_DEMAND_RFO, |
| SKL_OFFCORE_REQUESTS_ALL_DATA_RD, |
| SKL_OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_RD, |
| SKL_OFFCORE_REQUESTS_ALL_REQUESTS, |
| SKL_OFFCORE_REQUEST_BUFFER_SQ_FULL) |
| |
| DEF_CATEGORY(IPM_CATEGORY_BR_MISP, 31, "br_misp", |
| SKL_BR_MISP_RETIRED_ALL_BRANCHES, |
| SKL_BR_MISP_RETIRED_CONDITIONAL, |
| SKL_BR_MISP_RETIRED_MACRO, |
| SKL_BR_MISP_RETIRED_NEAR_TAKEN) |
| |
| DEF_CATEGORY(IPM_CATEGORY_HW_INTERRUPTS, 32, "hw_interrupts", |
| SKL_HW_INTERRUPTS_RECEIVED) |
| |
| DEF_CATEGORY(IPM_CATEGORY_MEM_RETIRED, 33, "mem_retired_summary", |
| SKL_MEM_INST_RETIRED_LOCKED_LOADS, |
| SKL_MEM_INST_RETIRED_ALL_LOADS, |
| SKL_MEM_INST_RETIRED_ALL_STORES) |
| |
| DEF_CATEGORY(IPM_CATEGORY_MEM_RETIRED_HIT, 34, "mem_retired_hit", |
| SKL_MEM_LOAD_RETIRED_L1_HIT, |
| SKL_MEM_LOAD_RETIRED_L2_HIT, |
| SKL_MEM_LOAD_RETIRED_L3_HIT) |
| |
| DEF_CATEGORY(IPM_CATEGORY_MEM_RETIRED_MISS, 35, "mem_retired_miss", |
| SKL_MEM_LOAD_RETIRED_L1_MISS, |
| SKL_MEM_LOAD_RETIRED_L2_MISS, |
| SKL_MEM_LOAD_RETIRED_L3_MISS) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L3_HIT_RETIRED_XSNP, 36, "l3_hit_retired_xsnp", |
| SKL_MEM_LOAD_L3_HIT_RETIRED_XSNP_MISS, |
| SKL_MEM_LOAD_L3_HIT_RETIRED_XSNP_HIT, |
| SKL_MEM_LOAD_L3_HIT_RETIRED_XSNP_HITM, |
| SKL_MEM_LOAD_L3_HIT_RETIRED_XSNP_NONE) |
| |
| DEF_CATEGORY(IPM_CATEGORY_L2_LINES, 37, "l2_lines", |
| SKL_L2_TRANS_L2_WB, |
| SKL_L2_LINES_IN_ALL) |
| |
| #undef DEF_CATEGORY |
