Add Intel SHA instructions.
Contributed by: Mark Charney @ Intel
diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py
index ceed184..c4aedf0 100755
--- a/modules/arch/x86/gen_x86_insn.py
+++ b/modules/arch/x86/gen_x86_insn.py
@@ -39,7 +39,7 @@
"SSE3", "SVM", "PadLock", "SSSE3", "SSE41", "SSE42", "SSE4a", "SSE5",
"AVX", "FMA", "AES", "CLMUL", "MOVBE", "XOP", "FMA4", "F16C",
"FSGSBASE", "RDRAND", "XSAVEOPT", "EPTVPID", "SMX", "AVX2", "BMI1",
- "BMI2", "INVPCID", "LZCNT", "TBM", "TSX"]
+ "BMI2", "INVPCID", "LZCNT", "TBM", "TSX", "SHA"]
unordered_cpu_features = ["Priv", "Prot", "Undoc", "Obs"]
# Predefined VEX prefix field values
@@ -8056,6 +8056,55 @@
Operand(type="Mem", size=128, relaxed=True, dest="EA")])
add_insn("invpcid", "invpcid")
+
+#####################################################################
+add_group("intel_SHA1MSG1",
+ cpu=["SHA"],
+ opcode=[0x0F, 0x38, 0xC9],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDRM", size=128, dest="EA", relaxed=True)])
+add_group("intel_SHA1MSG2",
+ cpu=["SHA"],
+ opcode=[0x0F, 0x38, 0xCA],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDRM", size=128, dest="EA", relaxed=True)])
+add_group("intel_SHA1NEXTE",
+ cpu=["SHA"],
+ opcode=[0x0F, 0x38, 0xC8],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDRM", size=128, dest="EA", relaxed=True)])
+add_group("intel_SHA1RNDS4",
+ cpu=["SHA"],
+ opcode=[0x0F, 0x3A, 0xCC],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDRM", size=128, dest="EA", relaxed=True),
+ Operand(type="Imm", size=8, dest="Imm", relaxed=True)])
+add_group("intel_SHA256MSG1",
+ cpu=["SHA"],
+ opcode=[0x0F, 0x38, 0xCC],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDRM", size=128, dest="EA", relaxed=True)])
+add_group("intel_SHA256MSG2",
+ cpu=["SHA"],
+ opcode=[0x0F, 0x38, 0xCD],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDRM", size=128, dest="EA", relaxed=True)])
+add_group("intel_SHA256RNDS2",
+ cpu=["SHA"],
+ opcode=[0x0F, 0x38, 0xCB],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="EA")])
+
+
+add_insn("SHA1MSG1", "intel_SHA1MSG1")
+add_insn("SHA1MSG2", "intel_SHA1MSG2")
+add_insn("SHA1NEXTE", "intel_SHA1NEXTE")
+add_insn("SHA1RNDS4", "intel_SHA1RNDS4")
+add_insn("SHA256MSG1", "intel_SHA256MSG1")
+add_insn("SHA256MSG2", "intel_SHA256MSG2")
+add_insn("SHA256RNDS2", "intel_SHA256RNDS2")
+
+
#####################################################################
# AMD trailing bit manipulation (TBM)
#####################################################################
diff --git a/modules/arch/x86/x86arch.h b/modules/arch/x86/x86arch.h
index 14b2b2e..7ad1046 100644
--- a/modules/arch/x86/x86arch.h
+++ b/modules/arch/x86/x86arch.h
@@ -85,6 +85,7 @@
#define CPU_LZCNT 51 /* Intel LZCNT instruction */
#define CPU_TBM 52 /* AMD TBM instruction */
#define CPU_TSX 53 /* Intel TSX instructions */
+#define CPU_SHA 54 /* Intel SHA instructions */
enum x86_parser_type {
X86_PARSER_NASM = 0,
diff --git a/modules/arch/x86/x86cpu.gperf b/modules/arch/x86/x86cpu.gperf
index 3d49574..d680866 100644
--- a/modules/arch/x86/x86cpu.gperf
+++ b/modules/arch/x86/x86cpu.gperf
@@ -402,6 +402,8 @@
nolzcnt, x86_cpu_clear, CPU_LZCNT
tbm, x86_cpu_set, CPU_TBM
notbm, x86_cpu_clear, CPU_TBM
+sha, x86_cpu_set, CPU_SHA
+nosha, x86_cpu_clear, CPU_SHA
# Change NOP patterns
basicnop, x86_nop, X86_NOP_BASIC
intelnop, x86_nop, X86_NOP_INTEL
