| commit | 4a643d98c388727e73aebbe626a7379c6fddbbbe | [log] [tgz] |
|---|---|---|
| author | Jean-Marc Valin <jmvalin@jmvalin.ca> | Fri Sep 14 16:27:03 2018 -0400 |
| committer | Jean-Marc Valin <jmvalin@jmvalin.ca> | Fri Sep 14 16:27:03 2018 -0400 |
| tree | 37dc822e588dd4e9566696126103b477c02f2cc2 | |
| parent | c6d977a966ccdb9ea684d8650cc6f8cccfedf8d7 [diff] |
Fixes packet parsing for 16-bit CPUs Without that change, a very long (> 682 ms) illegal packet could trigger a wrap-around in the test and be accepted as valid. Only 16-bit architectures (e.g. TI C5x) were affected.