commit fddbbe5f018affa87a4cb925f7a1627298cc2ebf
author Slawomir Cygan <slawomir.cygan@intel.com> Thu May 07 17:47:08 2020 +0200
committer Alexander Galazin <Alexander.Galazin@arm.com> Thu May 14 11:12:57 2020 -0400
tree 1d6ad8c4313682062b192b743f287fbd8ca4d97c
parent fc9f58142d09c2a796a4134d3eb496f69aa35bb8

Add missing barrier to HOST in memory_barrier test

The test was lacking a barrier between device write access and
validation of the data on host.

Components: Vulkan

VK-GL-CTS Issue: 2359

Affects: dEQP-VK.memory_model.message_passing.*

Change-Id: Ia75277aaa2c7e25bff807cd3c6ebe14513403bfc

external/vulkancts/modules/vulkan/memory_model/vktMemoryModelMessagePassing.cpp

diff --git a/external/vulkancts/modules/vulkan/memory_model/vktMemoryModelMessagePassing.cpp b/external/vulkancts/modules/vulkan/memory_model/vktMemoryModelMessagePassing.cpp
index f101267..02b4ad2 100644
--- a/external/vulkancts/modules/vulkan/memory_model/vktMemoryModelMessagePassing.cpp
+++ b/external/vulkancts/modules/vulkan/memory_model/vktMemoryModelMessagePassing.cpp
@@ -1589,7 +1589,13 @@
 		}
 
 		if (x == NUM_SUBMITS - 1)
+		{
 			vk.cmdCopyBuffer(*cmdBuffer, **buffers[2], **copyBuffer, 1, &copyParams);
+			memBarrier.srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT;
+			memBarrier.dstAccessMask = VK_ACCESS_HOST_READ_BIT;
+			vk.cmdPipelineBarrier(*cmdBuffer, VK_PIPELINE_STAGE_TRANSFER_BIT, VK_PIPELINE_STAGE_HOST_BIT,
+				0, 1, &memBarrier, 0, DE_NULL, 0, DE_NULL);
+		}
 
 		endCommandBuffer(vk, *cmdBuffer);