| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_clamp_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_invert_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_invert_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_invert_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_invert_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_inc_wrap_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_inc_wrap_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_inc_wrap_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_inc_wrap_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_inc_wrap_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_inc_wrap_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_wrap_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_wrap_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_wrap_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_wrap_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_wrap_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_back_xt_dec_wrap_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_keep_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_zero_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_replace_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_inc_clamp_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_inc_clamp_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_dec_clamp_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_dec_clamp_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_invert_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_inc_wrap_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_inc_wrap_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_dec_wrap_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_dec_wrap_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xf_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_keep_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_keep_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_keep_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_zero_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_zero_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_zero_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_replace_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_replace_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_replace_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_clamp_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_clamp_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_clamp_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_clamp_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_clamp_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_clamp_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_clamp_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_clamp_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_clamp_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_clamp_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_invert_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_invert_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_invert_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_wrap_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_wrap_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_wrap_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_wrap_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_wrap_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_inc_wrap_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_wrap_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_wrap_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_wrap_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_wrap_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_lt_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_eq_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_keep_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_keep_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_zero_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_zero_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_replace_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_replace_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_clamp_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_clamp_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_clamp_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_clamp_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_clamp_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_clamp_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_invert_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_invert_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_wrap_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_wrap_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_wrap_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_wrap_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_wrap_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_wrap_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_le_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_keep_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_keep_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_keep_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_zero_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_zero_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_zero_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_replace_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_replace_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_replace_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_clamp_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_clamp_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_clamp_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_clamp_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_clamp_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_clamp_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_clamp_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_clamp_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_clamp_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_clamp_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_invert_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_invert_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_invert_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_wrap_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_wrap_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_wrap_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_inc_wrap_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_wrap_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_wrap_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_wrap_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_wrap_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_wrap_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_gt_dec_wrap_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_keep_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_keep_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_zero_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_zero_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_replace_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_replace_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_clamp_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_clamp_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_clamp_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_clamp_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_clamp_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_clamp_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_invert_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_invert_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_wrap_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_wrap_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_wrap_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_wrap_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_wrap_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_ge_dec_wrap_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_keep_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_keep_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_keep_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_keep_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_zero_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_zero_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_zero_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_zero_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_replace_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_replace_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_replace_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_replace_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_clamp_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_clamp_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_clamp_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_clamp_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_clamp_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_clamp_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_clamp_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_clamp_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_clamp_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_clamp_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_clamp_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_clamp_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_invert_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_invert_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_invert_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_invert_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_wrap_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_wrap_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_wrap_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_wrap_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_wrap_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_wrap_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_wrap_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_wrap_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_wrap_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_wrap_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_wrap_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_single_xt_dec_wrap_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_keep_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_zero_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_replace_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_inc_clamp_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_inc_clamp_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_dec_clamp_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_dec_clamp_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_invert_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_inc_wrap_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_inc_wrap_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_dec_wrap_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_dec_wrap_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xf_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_keep_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_keep_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_keep_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_zero_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_zero_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_zero_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_replace_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_replace_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_replace_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_clamp_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_clamp_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_clamp_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_clamp_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_clamp_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_clamp_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_clamp_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_clamp_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_clamp_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_clamp_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_invert_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_invert_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_invert_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_wrap_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_wrap_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_wrap_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_wrap_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_wrap_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_inc_wrap_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_wrap_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_wrap_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_wrap_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_wrap_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_lt_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_eq_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_keep_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_keep_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_zero_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_zero_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_replace_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_replace_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_clamp_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_clamp_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_clamp_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_clamp_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_clamp_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_clamp_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_invert_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_invert_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_wrap_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_wrap_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_wrap_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_wrap_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_wrap_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_wrap_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_le_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_keep_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_keep_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_keep_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_zero_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_zero_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_zero_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_replace_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_replace_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_replace_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_clamp_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_clamp_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_clamp_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_clamp_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_clamp_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_clamp_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_clamp_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_clamp_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_clamp_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_clamp_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_invert_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_invert_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_invert_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_wrap_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_wrap_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_wrap_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_inc_wrap_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_wrap_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_wrap_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_wrap_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_wrap_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_wrap_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_gt_dec_wrap_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_keep_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_keep_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_zero_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_zero_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_replace_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_replace_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_clamp_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_clamp_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_clamp_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_clamp_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_clamp_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_clamp_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_invert_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_invert_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_wrap_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_wrap_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_wrap_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_wrap_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_wrap_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_ge_dec_wrap_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_keep_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_keep_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_keep_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_keep_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_zero_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_zero_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_zero_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_zero_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_replace_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_replace_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_replace_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_replace_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_clamp_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_clamp_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_clamp_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_clamp_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_clamp_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_clamp_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_clamp_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_clamp_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_clamp_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_clamp_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_clamp_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_clamp_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_invert_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_invert_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_invert_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_invert_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_wrap_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_wrap_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_wrap_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_wrap_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_wrap_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_wrap_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_wrap_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_wrap_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_wrap_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_wrap_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_wrap_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.stencil_state_face_both_dual_xt_dec_wrap_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.vertex_input |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.cull_none |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.cull_back |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.cull_front |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.cull_front_and_back |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.front_face_cw |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.front_face_ccw |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.front_face_cw_reversed |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.front_face_ccw_reversed |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.disable_raster |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.enable_raster |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.logic_op_or |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.prim_restart_enable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.patch_control_points |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.topology_triangle |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.topology_line |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.topology_triangle_geom |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.topology_line_geom |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.2_viewports |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.1_full_viewport |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.2_viewports_switch |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.2_viewports_switch_clean |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.2_scissors |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.1_full_scissor |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.2_scissors_switch |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.2_scissors_switch_clean |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stride |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stride_with_offset |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stride_with_offset_and_padding |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.large_stride |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.large_stride_with_offset |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.large_stride_with_offset_and_padding |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_test_enable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_test_disable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_write_enable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_write_disable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_bias_enable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_bias_disable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_never |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_less |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_greater |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_equal |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_less_equal_less |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_less_equal_equal |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_less_equal_less_then_equal |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_greater_equal_greater |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_greater_equal_equal |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_greater_equal_greater_then_equal |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_not_equal |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_always_equal |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_always_less |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_compare_always_greater |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_bounds_test_enable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.depth_bounds_test_disable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_test_enable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_test_disable |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_keep_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_zero_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_replace_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_inc_clamp_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_inc_clamp_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_dec_clamp_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_dec_clamp_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_invert_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_inc_wrap_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_inc_wrap_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_dec_wrap_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_dec_wrap_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_xf_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_keep_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_keep_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_keep_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_zero_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_zero_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_zero_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_replace_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_replace_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_replace_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_clamp_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_clamp_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_clamp_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_clamp_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_clamp_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_clamp_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_clamp_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_clamp_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_clamp_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_clamp_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_invert_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_invert_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_invert_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_wrap_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_wrap_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_wrap_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_wrap_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_wrap_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_inc_wrap_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_wrap_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_wrap_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_wrap_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_wrap_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_lt_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_eq_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_keep_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_keep_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_keep_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_zero_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_zero_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_zero_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_replace_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_replace_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_replace_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_clamp_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_clamp_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_clamp_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_clamp_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_clamp_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_clamp_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_clamp_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_clamp_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_clamp_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_invert_clear_102_ref_101_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_invert_clear_102_ref_101_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_invert_clear_102_ref_103_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_wrap_clear_254_ref_253_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_wrap_clear_254_ref_253_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_wrap_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_wrap_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_wrap_clear_254_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_wrap_clear_255_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_wrap_clear_255_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_wrap_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_inc_wrap_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_wrap_clear_1_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_wrap_clear_1_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_wrap_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_wrap_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_wrap_clear_1_ref_2_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_wrap_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_wrap_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_le_dec_wrap_clear_0_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_keep_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_keep_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_keep_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_zero_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_zero_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_zero_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_replace_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_replace_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_replace_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_clamp_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_clamp_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_clamp_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_clamp_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_clamp_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_clamp_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_clamp_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_clamp_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_clamp_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_clamp_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_invert_clear_102_ref_102_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_invert_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_invert_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_wrap_clear_254_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_wrap_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_wrap_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_wrap_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_inc_wrap_clear_255_ref_255_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_wrap_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_wrap_clear_1_ref_1_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_wrap_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_wrap_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_wrap_clear_0_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_wrap_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_gt_dec_wrap_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_keep_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_keep_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_keep_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_keep_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_keep_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_zero_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_zero_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_zero_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_zero_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_zero_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_replace_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_replace_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_replace_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_replace_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_replace_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_inc_clamp_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_inc_clamp_clear_254_ref_254_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_inc_clamp_clear_254_ref_254_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_inc_clamp_clear_254_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_inc_clamp_clear_254_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_inc_clamp_clear_255_ref_254_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_inc_clamp_clear_255_ref_255_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_inc_clamp_clear_255_ref_255_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_dec_clamp_clear_1_ref_0_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_dec_clamp_clear_1_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_dec_clamp_clear_1_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_dec_clamp_clear_1_ref_2_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_dec_clamp_clear_1_ref_2_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_dec_clamp_clear_0_ref_0_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_dec_clamp_clear_0_ref_0_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_dec_clamp_clear_0_ref_1_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_dec_clamp_clear_0_ref_1_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_invert_clear_102_ref_101_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_invert_clear_102_ref_102_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_invert_clear_102_ref_102_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_invert_clear_102_ref_103_pass |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_invert_clear_102_ref_103_depthfail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_inc_wrap_clear_254_ref_253_fail |
| dEQP-VK.pipeline.extended_dynamic_state.before_draw.stencil_state_face_front_ge_inc_wrap_clear_254_ref_254_pass |