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fuchsia / third_party / vulkan-cts / 178c5a1719c356fd660466c45a7cb1ad2d0074ed / . / external / vulkancts / modules / vulkan / spirv_assembly / vktSpvAsmInstructionTests.cpp
blob: 7f5ce60644d34e7a5ecb0ecc3e409e393eadc9ef [file] [log] [blame]
/*-------------------------------------------------------------------------
* Vulkan Conformance Tests
* ------------------------
*
* Copyright (c) 2015 Google Inc.
* Copyright (c) 2016 The Khronos Group Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*//*!
* \file
* \brief SPIR-V Assembly Tests for Instructions (special opcode/operand)
*//*--------------------------------------------------------------------*/
#include "vktSpvAsmInstructionTests.hpp"
#include "tcuCommandLine.hpp"
#include "tcuFormatUtil.hpp"
#include "tcuFloat.hpp"
#include "tcuFloatFormat.hpp"
#include "tcuRGBA.hpp"
#include "tcuStringTemplate.hpp"
#include "tcuTestLog.hpp"
#include "tcuVectorUtil.hpp"
#include "tcuInterval.hpp"
#include "vkDefs.hpp"
#include "vkDeviceUtil.hpp"
#include "vkMemUtil.hpp"
#include "vkPlatform.hpp"
#include "vkPrograms.hpp"
#include "vkQueryUtil.hpp"
#include "vkRef.hpp"
#include "vkRefUtil.hpp"
#include "vkStrUtil.hpp"
#include "vkTypeUtil.hpp"
#include "deStringUtil.hpp"
#include "deUniquePtr.hpp"
#include "deMath.h"
#include "tcuStringTemplate.hpp"
#include "vktSpvAsmCrossStageInterfaceTests.hpp"
#include "vktSpvAsm8bitStorageTests.hpp"
#include "vktSpvAsm16bitStorageTests.hpp"
#include "vktSpvAsmUboMatrixPaddingTests.hpp"
#include "vktSpvAsmConditionalBranchTests.hpp"
#include "vktSpvAsmIndexingTests.hpp"
#include "vktSpvAsmImageSamplerTests.hpp"
#include "vktSpvAsmComputeShaderCase.hpp"
#include "vktSpvAsmComputeShaderTestUtil.hpp"
#include "vktSpvAsmFloatControlsTests.hpp"
#include "vktSpvAsmGraphicsShaderTestUtil.hpp"
#include "vktSpvAsmVariablePointersTests.hpp"
#include "vktSpvAsmVariableInitTests.hpp"
#include "vktSpvAsmPointerParameterTests.hpp"
#include "vktSpvAsmSpirvVersionTests.hpp"
#include "vktTestCaseUtil.hpp"
#include "vktSpvAsmLoopDepLenTests.hpp"
#include "vktSpvAsmLoopDepInfTests.hpp"
#include "vktSpvAsmCompositeInsertTests.hpp"
#include "vktSpvAsmVaryingNameTests.hpp"
#include "vktSpvAsmWorkgroupMemoryTests.hpp"
#include <cmath>
#include <limits>
#include <map>
#include <string>
#include <sstream>
#include <utility>
#include <stack>
namespace vkt
{
namespace SpirVAssembly
{
namespace
{
using namespace vk;
using std::map;
using std::string;
using std::vector;
using tcu::IVec3;
using tcu::IVec4;
using tcu::RGBA;
using tcu::TestLog;
using tcu::TestStatus;
using tcu::Vec4;
using de::UniquePtr;
using tcu::StringTemplate;
using tcu::Vec4;
const bool TEST_WITH_NAN = true;
const bool TEST_WITHOUT_NAN = false;
template<typename T>
static void fillRandomScalars (de::Random& rnd, T minValue, T maxValue, void* dst, int numValues, int offset = 0)
{
T* const typedPtr = (T*)dst;
for (int ndx = 0; ndx < numValues; ndx++)
typedPtr[offset + ndx] = randomScalar<T>(rnd, minValue, maxValue);
}
// Filter is a function that returns true if a value should pass, false otherwise.
template<typename T, typename FilterT>
static void fillRandomScalars (de::Random& rnd, T minValue, T maxValue, void* dst, int numValues, FilterT filter, int offset = 0)
{
T* const typedPtr = (T*)dst;
T value;
for (int ndx = 0; ndx < numValues; ndx++)
{
do
value = randomScalar<T>(rnd, minValue, maxValue);
while (!filter(value));
typedPtr[offset + ndx] = value;
}
}
// Gets a 64-bit integer with a more logarithmic distribution
deInt64 randomInt64LogDistributed (de::Random& rnd)
{
deInt64 val = rnd.getUint64();
val &= (1ull << rnd.getInt(1, 63)) - 1;
if (rnd.getBool())
val = -val;
return val;
}
static void fillRandomInt64sLogDistributed (de::Random& rnd, vector<deInt64>& dst, int numValues)
{
for (int ndx = 0; ndx < numValues; ndx++)
dst[ndx] = randomInt64LogDistributed(rnd);
}
template<typename FilterT>
static void fillRandomInt64sLogDistributed (de::Random& rnd, vector<deInt64>& dst, int numValues, FilterT filter)
{
for (int ndx = 0; ndx < numValues; ndx++)
{
deInt64 value;
do {
value = randomInt64LogDistributed(rnd);
} while (!filter(value));
dst[ndx] = value;
}
}
inline bool filterNonNegative (const deInt64 value)
{
return value >= 0;
}
inline bool filterPositive (const deInt64 value)
{
return value > 0;
}
inline bool filterNotZero (const deInt64 value)
{
return value != 0;
}
static void floorAll (vector<float>& values)
{
for (size_t i = 0; i < values.size(); i++)
values[i] = deFloatFloor(values[i]);
}
static void floorAll (vector<Vec4>& values)
{
for (size_t i = 0; i < values.size(); i++)
values[i] = floor(values[i]);
}
struct CaseParameter
{
const char* name;
string param;
CaseParameter (const char* case_, const string& param_) : name(case_), param(param_) {}
};
// Assembly code used for testing LocalSize, OpNop, OpConstant{Null|Composite}, Op[No]Line, OpSource[Continued], OpSourceExtension, OpUndef is based on GLSL source code:
//
// #version 430
//
// layout(std140, set = 0, binding = 0) readonly buffer Input {
// float elements[];
// } input_data;
// layout(std140, set = 0, binding = 1) writeonly buffer Output {
// float elements[];
// } output_data;
//
// layout (local_size_x = 1, local_size_y = 1, local_size_z = 1) in;
//
// void main() {
// uint x = gl_GlobalInvocationID.x;
// output_data.elements[x] = -input_data.elements[x];
// }
static string getAsmForLocalSizeTest(bool useLiteralLocalSize, bool useSpecConstantWorkgroupSize, IVec3 workGroupSize, deUint32 ndx)
{
std::ostringstream out;
out << getComputeAsmShaderPreambleWithoutLocalSize();
if (useLiteralLocalSize)
{
out << "OpExecutionMode %main LocalSize "
<< workGroupSize.x() << " " << workGroupSize.y() << " " << workGroupSize.z() << "\n";
}
out << "OpSource GLSL 430\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n";
if (useSpecConstantWorkgroupSize)
{
out << "OpDecorate %spec_0 SpecId 100\n"
<< "OpDecorate %spec_1 SpecId 101\n"
<< "OpDecorate %spec_2 SpecId 102\n"
<< "OpDecorate %gl_WorkGroupSize BuiltIn WorkgroupSize\n";
}
out << getComputeAsmInputOutputBufferTraits()
<< getComputeAsmCommonTypes()
<< getComputeAsmInputOutputBuffer()
<< "%id = OpVariable %uvec3ptr Input\n"
<< "%zero = OpConstant %i32 0 \n";
if (useSpecConstantWorkgroupSize)
{
out << "%spec_0 = OpSpecConstant %u32 "<< workGroupSize.x() << "\n"
<< "%spec_1 = OpSpecConstant %u32 "<< workGroupSize.y() << "\n"
<< "%spec_2 = OpSpecConstant %u32 "<< workGroupSize.z() << "\n"
<< "%gl_WorkGroupSize = OpSpecConstantComposite %uvec3 %spec_0 %spec_1 %spec_2\n";
}
out << "%main = OpFunction %void None %voidf\n"
<< "%label = OpLabel\n"
<< "%idval = OpLoad %uvec3 %id\n"
<< "%ndx = OpCompositeExtract %u32 %idval " << ndx << "\n"
"%inloc = OpAccessChain %f32ptr %indata %zero %ndx\n"
"%inval = OpLoad %f32 %inloc\n"
"%neg = OpFNegate %f32 %inval\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %ndx\n"
" OpStore %outloc %neg\n"
" OpReturn\n"
" OpFunctionEnd\n";
return out.str();
}
tcu::TestCaseGroup* createLocalSizeGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "localsize", ""));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const deUint32 numElements = 64u;
vector<float> positiveFloats (numElements, 0);
vector<float> negativeFloats (numElements, 0);
fillRandomScalars(rnd, 1.f, 100.f, &positiveFloats[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
negativeFloats[ndx] = -positiveFloats[ndx];
spec.inputs.push_back(BufferSp(new Float32Buffer(positiveFloats)));
spec.outputs.push_back(BufferSp(new Float32Buffer(negativeFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.assembly = getAsmForLocalSizeTest(true, false, IVec3(1, 1, 1), 0u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "literal_localsize", "", spec));
spec.assembly = getAsmForLocalSizeTest(true, true, IVec3(1, 1, 1), 0u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "literal_and_specid_localsize", "", spec));
spec.assembly = getAsmForLocalSizeTest(false, true, IVec3(1, 1, 1), 0u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "specid_localsize", "", spec));
spec.numWorkGroups = IVec3(1, 1, 1);
spec.assembly = getAsmForLocalSizeTest(true, false, IVec3(numElements, 1, 1), 0u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "literal_localsize_x", "", spec));
spec.assembly = getAsmForLocalSizeTest(true, true, IVec3(numElements, 1, 1), 0u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "literal_and_specid_localsize_x", "", spec));
spec.assembly = getAsmForLocalSizeTest(false, true, IVec3(numElements, 1, 1), 0u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "specid_localsize_x", "", spec));
spec.assembly = getAsmForLocalSizeTest(true, false, IVec3(1, numElements, 1), 1u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "literal_localsize_y", "", spec));
spec.assembly = getAsmForLocalSizeTest(true, true, IVec3(1, numElements, 1), 1u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "literal_and_specid_localsize_y", "", spec));
spec.assembly = getAsmForLocalSizeTest(false, true, IVec3(1, numElements, 1), 1u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "specid_localsize_y", "", spec));
spec.assembly = getAsmForLocalSizeTest(true, false, IVec3(1, 1, numElements), 2u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "literal_localsize_z", "", spec));
spec.assembly = getAsmForLocalSizeTest(true, true, IVec3(1, 1, numElements), 2u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "literal_and_specid_localsize_z", "", spec));
spec.assembly = getAsmForLocalSizeTest(false, true, IVec3(1, 1, numElements), 2u);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "specid_localsize_z", "", spec));
return group.release();
}
tcu::TestCaseGroup* createOpNopGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opnop", "Test the OpNop instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 100;
vector<float> positiveFloats (numElements, 0);
vector<float> negativeFloats (numElements, 0);
fillRandomScalars(rnd, 1.f, 100.f, &positiveFloats[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
negativeFloats[ndx] = -positiveFloats[ndx];
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"OpSource GLSL 430\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
+ string(getComputeAsmInputOutputBufferTraits()) + string(getComputeAsmCommonTypes())
+ string(getComputeAsmInputOutputBuffer()) +
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
" OpNop\n" // Inside a function body
"%inloc = OpAccessChain %f32ptr %indata %zero %x\n"
"%inval = OpLoad %f32 %inloc\n"
"%neg = OpFNegate %f32 %inval\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
" OpStore %outloc %neg\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(positiveFloats)));
spec.outputs.push_back(BufferSp(new Float32Buffer(negativeFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "all", "OpNop appearing at different places", spec));
return group.release();
}
template<bool nanSupported>
bool compareFUnord (const std::vector<Resource>& inputs, const vector<AllocationSp>& outputAllocs, const std::vector<Resource>& expectedOutputs, TestLog& log)
{
if (outputAllocs.size() != 1)
return false;
vector<deUint8> input1Bytes;
vector<deUint8> input2Bytes;
vector<deUint8> expectedBytes;
inputs[0].getBytes(input1Bytes);
inputs[1].getBytes(input2Bytes);
expectedOutputs[0].getBytes(expectedBytes);
const deInt32* const expectedOutputAsInt = reinterpret_cast<const deInt32*>(&expectedBytes.front());
const deInt32* const outputAsInt = static_cast<const deInt32*>(outputAllocs[0]->getHostPtr());
const float* const input1AsFloat = reinterpret_cast<const float*>(&input1Bytes.front());
const float* const input2AsFloat = reinterpret_cast<const float*>(&input2Bytes.front());
bool returnValue = true;
for (size_t idx = 0; idx < expectedBytes.size() / sizeof(deInt32); ++idx)
{
if (!nanSupported && (tcu::Float32(input1AsFloat[idx]).isNaN() || tcu::Float32(input2AsFloat[idx]).isNaN()))
continue;
if (outputAsInt[idx] != expectedOutputAsInt[idx])
{
log << TestLog::Message << "ERROR: Sub-case failed. inputs: " << input1AsFloat[idx] << "," << input2AsFloat[idx] << " output: " << outputAsInt[idx]<< " expected output: " << expectedOutputAsInt[idx] << TestLog::EndMessage;
returnValue = false;
}
}
return returnValue;
}
typedef VkBool32 (*compareFuncType) (float, float);
struct OpFUnordCase
{
const char* name;
const char* opCode;
compareFuncType compareFunc;
OpFUnordCase (const char* _name, const char* _opCode, compareFuncType _compareFunc)
: name (_name)
, opCode (_opCode)
, compareFunc (_compareFunc) {}
};
#define ADD_OPFUNORD_CASE(NAME, OPCODE, OPERATOR) \
do { \
struct compare_##NAME { static VkBool32 compare(float x, float y) { return (x OPERATOR y) ? VK_TRUE : VK_FALSE; } }; \
cases.push_back(OpFUnordCase(#NAME, OPCODE, compare_##NAME::compare)); \
} while (deGetFalse())
tcu::TestCaseGroup* createOpFUnordGroup (tcu::TestContext& testCtx, const bool nanSupported)
{
const string nan = nanSupported ? "_nan" : "";
const string groupName = "opfunord" + nan;
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, groupName.c_str(), "Test the OpFUnord* opcodes"));
de::Random rnd (deStringHash(group->getName()));
const int numElements = 100;
vector<OpFUnordCase> cases;
string extensions = nanSupported ? "OpExtension \"SPV_KHR_float_controls\"\n" : "";
string capabilities = nanSupported ? "OpCapability SignedZeroInfNanPreserve\n" : "";
string exeModes = nanSupported ? "OpExecutionMode %main SignedZeroInfNanPreserve 32\n" : "";
const StringTemplate shaderTemplate (
string(getComputeAsmShaderPreamble(capabilities, extensions, exeModes)) +
"OpSource GLSL 430\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %buf BufferBlock\n"
"OpDecorate %buf2 BufferBlock\n"
"OpDecorate %indata1 DescriptorSet 0\n"
"OpDecorate %indata1 Binding 0\n"
"OpDecorate %indata2 DescriptorSet 0\n"
"OpDecorate %indata2 Binding 1\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 2\n"
"OpDecorate %f32arr ArrayStride 4\n"
"OpDecorate %i32arr ArrayStride 4\n"
"OpMemberDecorate %buf 0 Offset 0\n"
"OpMemberDecorate %buf2 0 Offset 0\n"
+ string(getComputeAsmCommonTypes()) +
"%buf = OpTypeStruct %f32arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata1 = OpVariable %bufptr Uniform\n"
"%indata2 = OpVariable %bufptr Uniform\n"
"%buf2 = OpTypeStruct %i32arr\n"
"%buf2ptr = OpTypePointer Uniform %buf2\n"
"%outdata = OpVariable %buf2ptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%consti1 = OpConstant %i32 1\n"
"%constf1 = OpConstant %f32 1.0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc1 = OpAccessChain %f32ptr %indata1 %zero %x\n"
"%inval1 = OpLoad %f32 %inloc1\n"
"%inloc2 = OpAccessChain %f32ptr %indata2 %zero %x\n"
"%inval2 = OpLoad %f32 %inloc2\n"
"%outloc = OpAccessChain %i32ptr %outdata %zero %x\n"
"%result = ${OPCODE} %bool %inval1 %inval2\n"
"%int_res = OpSelect %i32 %result %consti1 %zero\n"
" OpStore %outloc %int_res\n"
" OpReturn\n"
" OpFunctionEnd\n");
ADD_OPFUNORD_CASE(equal, "OpFUnordEqual", ==);
ADD_OPFUNORD_CASE(less, "OpFUnordLessThan", <);
ADD_OPFUNORD_CASE(lessequal, "OpFUnordLessThanEqual", <=);
ADD_OPFUNORD_CASE(greater, "OpFUnordGreaterThan", >);
ADD_OPFUNORD_CASE(greaterequal, "OpFUnordGreaterThanEqual", >=);
ADD_OPFUNORD_CASE(notequal, "OpFUnordNotEqual", !=);
for (size_t caseNdx = 0; caseNdx < cases.size(); ++caseNdx)
{
map<string, string> specializations;
ComputeShaderSpec spec;
const float NaN = std::numeric_limits<float>::quiet_NaN();
vector<float> inputFloats1 (numElements, 0);
vector<float> inputFloats2 (numElements, 0);
vector<deInt32> expectedInts (numElements, 0);
specializations["OPCODE"] = cases[caseNdx].opCode;
spec.assembly = shaderTemplate.specialize(specializations);
fillRandomScalars(rnd, 1.f, 100.f, &inputFloats1[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
{
switch (ndx % 6)
{
case 0: inputFloats2[ndx] = inputFloats1[ndx] + 1.0f; break;
case 1: inputFloats2[ndx] = inputFloats1[ndx] - 1.0f; break;
case 2: inputFloats2[ndx] = inputFloats1[ndx]; break;
case 3: inputFloats2[ndx] = NaN; break;
case 4: inputFloats2[ndx] = inputFloats1[ndx]; inputFloats1[ndx] = NaN; break;
case 5: inputFloats2[ndx] = NaN; inputFloats1[ndx] = NaN; break;
}
expectedInts[ndx] = tcu::Float32(inputFloats1[ndx]).isNaN() || tcu::Float32(inputFloats2[ndx]).isNaN() || cases[caseNdx].compareFunc(inputFloats1[ndx], inputFloats2[ndx]);
}
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats1)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats2)));
spec.outputs.push_back(BufferSp(new Int32Buffer(expectedInts)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.verifyIO = nanSupported ? &compareFUnord<true> : &compareFUnord<false>;
if (nanSupported)
{
spec.extensions.push_back("VK_KHR_shader_float_controls");
spec.requestedVulkanFeatures.floatControlsProperties.shaderSignedZeroInfNanPreserveFloat32 = DE_TRUE;
}
group->addChild(new SpvAsmComputeShaderCase(testCtx, cases[caseNdx].name, cases[caseNdx].name, spec));
}
return group.release();
}
struct OpAtomicCase
{
const char* name;
const char* assembly;
const char* retValAssembly;
OpAtomicType opAtomic;
deInt32 numOutputElements;
OpAtomicCase(const char* _name, const char* _assembly, const char* _retValAssembly, OpAtomicType _opAtomic, deInt32 _numOutputElements)
: name (_name)
, assembly (_assembly)
, retValAssembly (_retValAssembly)
, opAtomic (_opAtomic)
, numOutputElements (_numOutputElements) {}
};
tcu::TestCaseGroup* createOpAtomicGroup (tcu::TestContext& testCtx, bool useStorageBuffer, int numElements = 65535, bool verifyReturnValues = false)
{
std::string groupName ("opatomic");
if (useStorageBuffer)
groupName += "_storage_buffer";
if (verifyReturnValues)
groupName += "_return_values";
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, groupName.c_str(), "Test the OpAtomic* opcodes"));
vector<OpAtomicCase> cases;
const StringTemplate shaderTemplate (
string("OpCapability Shader\n") +
(useStorageBuffer ? "OpExtension \"SPV_KHR_storage_buffer_storage_class\"\n" : "") +
"OpMemoryModel Logical GLSL450\n"
"OpEntryPoint GLCompute %main \"main\" %id\n"
"OpExecutionMode %main LocalSize 1 1 1\n" +
"OpSource GLSL 430\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %buf ${BLOCK_DECORATION}\n"
"OpDecorate %indata DescriptorSet 0\n"
"OpDecorate %indata Binding 0\n"
"OpDecorate %i32arr ArrayStride 4\n"
"OpMemberDecorate %buf 0 Offset 0\n"
"OpDecorate %sumbuf ${BLOCK_DECORATION}\n"
"OpDecorate %sum DescriptorSet 0\n"
"OpDecorate %sum Binding 1\n"
"OpMemberDecorate %sumbuf 0 Coherent\n"
"OpMemberDecorate %sumbuf 0 Offset 0\n"
"${RETVAL_BUF_DECORATE}"
+ getComputeAsmCommonTypes("${BLOCK_POINTER_TYPE}") +
"%buf = OpTypeStruct %i32arr\n"
"%bufptr = OpTypePointer ${BLOCK_POINTER_TYPE} %buf\n"
"%indata = OpVariable %bufptr ${BLOCK_POINTER_TYPE}\n"
"%sumbuf = OpTypeStruct %i32arr\n"
"%sumbufptr = OpTypePointer ${BLOCK_POINTER_TYPE} %sumbuf\n"
"%sum = OpVariable %sumbufptr ${BLOCK_POINTER_TYPE}\n"
"${RETVAL_BUF_DECL}"
"%id = OpVariable %uvec3ptr Input\n"
"%minusone = OpConstant %i32 -1\n"
"%zero = OpConstant %i32 0\n"
"%one = OpConstant %u32 1\n"
"%two = OpConstant %i32 2\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc = OpAccessChain %i32ptr %indata %zero %x\n"
"%inval = OpLoad %i32 %inloc\n"
"%outloc = OpAccessChain %i32ptr %sum %zero ${INDEX}\n"
"${INSTRUCTION}"
"${RETVAL_ASSEMBLY}"
" OpReturn\n"
" OpFunctionEnd\n");
#define ADD_OPATOMIC_CASE(NAME, ASSEMBLY, RETVAL_ASSEMBLY, OPATOMIC, NUM_OUTPUT_ELEMENTS) \
do { \
DE_ASSERT((NUM_OUTPUT_ELEMENTS) == 1 || (NUM_OUTPUT_ELEMENTS) == numElements); \
cases.push_back(OpAtomicCase(#NAME, ASSEMBLY, RETVAL_ASSEMBLY, OPATOMIC, NUM_OUTPUT_ELEMENTS)); \
} while (deGetFalse())
#define ADD_OPATOMIC_CASE_1(NAME, ASSEMBLY, RETVAL_ASSEMBLY, OPATOMIC) ADD_OPATOMIC_CASE(NAME, ASSEMBLY, RETVAL_ASSEMBLY, OPATOMIC, 1)
#define ADD_OPATOMIC_CASE_N(NAME, ASSEMBLY, RETVAL_ASSEMBLY, OPATOMIC) ADD_OPATOMIC_CASE(NAME, ASSEMBLY, RETVAL_ASSEMBLY, OPATOMIC, numElements)
ADD_OPATOMIC_CASE_1(iadd, "%retv = OpAtomicIAdd %i32 %outloc %one %zero %inval\n",
" OpStore %retloc %retv\n", OPATOMIC_IADD );
ADD_OPATOMIC_CASE_1(isub, "%retv = OpAtomicISub %i32 %outloc %one %zero %inval\n",
" OpStore %retloc %retv\n", OPATOMIC_ISUB );
ADD_OPATOMIC_CASE_1(iinc, "%retv = OpAtomicIIncrement %i32 %outloc %one %zero\n",
" OpStore %retloc %retv\n", OPATOMIC_IINC );
ADD_OPATOMIC_CASE_1(idec, "%retv = OpAtomicIDecrement %i32 %outloc %one %zero\n",
" OpStore %retloc %retv\n", OPATOMIC_IDEC );
if (!verifyReturnValues)
{
ADD_OPATOMIC_CASE_N(load, "%inval2 = OpAtomicLoad %i32 %inloc %one %zero\n"
" OpStore %outloc %inval2\n", "", OPATOMIC_LOAD );
ADD_OPATOMIC_CASE_N(store, " OpAtomicStore %outloc %one %zero %inval\n", "", OPATOMIC_STORE );
}
ADD_OPATOMIC_CASE_N(compex, "%even = OpSMod %i32 %inval %two\n"
" OpStore %outloc %even\n"
"%retv = OpAtomicCompareExchange %i32 %outloc %one %zero %zero %minusone %zero\n",
" OpStore %retloc %retv\n", OPATOMIC_COMPEX );
#undef ADD_OPATOMIC_CASE
#undef ADD_OPATOMIC_CASE_1
#undef ADD_OPATOMIC_CASE_N
for (size_t caseNdx = 0; caseNdx < cases.size(); ++caseNdx)
{
map<string, string> specializations;
ComputeShaderSpec spec;
vector<deInt32> inputInts (numElements, 0);
vector<deInt32> expected (cases[caseNdx].numOutputElements, -1);
specializations["INDEX"] = (cases[caseNdx].numOutputElements == 1) ? "%zero" : "%x";
specializations["INSTRUCTION"] = cases[caseNdx].assembly;
specializations["BLOCK_DECORATION"] = useStorageBuffer ? "Block" : "BufferBlock";
specializations["BLOCK_POINTER_TYPE"] = useStorageBuffer ? "StorageBuffer" : "Uniform";
if (verifyReturnValues)
{
const StringTemplate blockDecoration (
"\n"
"OpDecorate %retbuf ${BLOCK_DECORATION}\n"
"OpDecorate %ret DescriptorSet 0\n"
"OpDecorate %ret Binding 2\n"
"OpMemberDecorate %retbuf 0 Offset 0\n\n");
const StringTemplate blockDeclaration (
"\n"
"%retbuf = OpTypeStruct %i32arr\n"
"%retbufptr = OpTypePointer ${BLOCK_POINTER_TYPE} %retbuf\n"
"%ret = OpVariable %retbufptr ${BLOCK_POINTER_TYPE}\n\n");
specializations["RETVAL_ASSEMBLY"] =
"%retloc = OpAccessChain %i32ptr %ret %zero %x\n"
+ std::string(cases[caseNdx].retValAssembly);
specializations["RETVAL_BUF_DECORATE"] = blockDecoration.specialize(specializations);
specializations["RETVAL_BUF_DECL"] = blockDeclaration.specialize(specializations);
}
else
{
specializations["RETVAL_ASSEMBLY"] = "";
specializations["RETVAL_BUF_DECORATE"] = "";
specializations["RETVAL_BUF_DECL"] = "";
}
spec.assembly = shaderTemplate.specialize(specializations);
if (useStorageBuffer)
spec.extensions.push_back("VK_KHR_storage_buffer_storage_class");
spec.inputs.push_back(BufferSp(new OpAtomicBuffer(numElements, cases[caseNdx].numOutputElements, cases[caseNdx].opAtomic, BUFFERTYPE_INPUT)));
spec.outputs.push_back(BufferSp(new OpAtomicBuffer(numElements, cases[caseNdx].numOutputElements, cases[caseNdx].opAtomic, BUFFERTYPE_EXPECTED)));
if (verifyReturnValues)
spec.outputs.push_back(BufferSp(new OpAtomicBuffer(numElements, cases[caseNdx].numOutputElements, cases[caseNdx].opAtomic, BUFFERTYPE_ATOMIC_RET)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
if (verifyReturnValues)
{
switch (cases[caseNdx].opAtomic)
{
case OPATOMIC_IADD:
spec.verifyIO = OpAtomicBuffer::compareWithRetvals<OPATOMIC_IADD>;
break;
case OPATOMIC_ISUB:
spec.verifyIO = OpAtomicBuffer::compareWithRetvals<OPATOMIC_ISUB>;
break;
case OPATOMIC_IINC:
spec.verifyIO = OpAtomicBuffer::compareWithRetvals<OPATOMIC_IINC>;
break;
case OPATOMIC_IDEC:
spec.verifyIO = OpAtomicBuffer::compareWithRetvals<OPATOMIC_IDEC>;
break;
case OPATOMIC_COMPEX:
spec.verifyIO = OpAtomicBuffer::compareWithRetvals<OPATOMIC_COMPEX>;
break;
default:
DE_FATAL("Unsupported OpAtomic type for return value verification");
}
}
group->addChild(new SpvAsmComputeShaderCase(testCtx, cases[caseNdx].name, cases[caseNdx].name, spec));
}
return group.release();
}
tcu::TestCaseGroup* createOpLineGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opline", "Test the OpLine instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 100;
vector<float> positiveFloats (numElements, 0);
vector<float> negativeFloats (numElements, 0);
fillRandomScalars(rnd, 1.f, 100.f, &positiveFloats[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
negativeFloats[ndx] = -positiveFloats[ndx];
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"%fname1 = OpString \"negateInputs.comp\"\n"
"%fname2 = OpString \"negateInputs\"\n"
"OpSource GLSL 430\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
+ string(getComputeAsmInputOutputBufferTraits()) +
"OpLine %fname1 0 0\n" // At the earliest possible position
+ string(getComputeAsmCommonTypes()) + string(getComputeAsmInputOutputBuffer()) +
"OpLine %fname1 0 1\n" // Multiple OpLines in sequence
"OpLine %fname2 1 0\n" // Different filenames
"OpLine %fname1 1000 100000\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"OpLine %fname1 1 1\n" // Before a function
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"OpLine %fname1 1 1\n" // In a function
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc = OpAccessChain %f32ptr %indata %zero %x\n"
"%inval = OpLoad %f32 %inloc\n"
"%neg = OpFNegate %f32 %inval\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
" OpStore %outloc %neg\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(positiveFloats)));
spec.outputs.push_back(BufferSp(new Float32Buffer(negativeFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "all", "OpLine appearing at different places", spec));
return group.release();
}
bool veryfiBinaryShader (const ProgramBinary& binary)
{
const size_t paternCount = 3u;
bool paternsCheck[paternCount] =
{
false, false, false
};
const string patersns[paternCount] =
{
"VULKAN CTS",
"Negative values",
"Date: 2017/09/21"
};
size_t paternNdx = 0u;
for (size_t ndx = 0u; ndx < binary.getSize(); ++ndx)
{
if (false == paternsCheck[paternNdx] &&
patersns[paternNdx][0] == static_cast<char>(binary.getBinary()[ndx]) &&
deMemoryEqual((const char*)&binary.getBinary()[ndx], &patersns[paternNdx][0], patersns[paternNdx].length()))
{
paternsCheck[paternNdx]= true;
paternNdx++;
if (paternNdx == paternCount)
break;
}
}
for (size_t ndx = 0u; ndx < paternCount; ++ndx)
{
if (!paternsCheck[ndx])
return false;
}
return true;
}
tcu::TestCaseGroup* createOpModuleProcessedGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opmoduleprocessed", "Test the OpModuleProcessed instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 10;
vector<float> positiveFloats (numElements, 0);
vector<float> negativeFloats (numElements, 0);
fillRandomScalars(rnd, 1.f, 100.f, &positiveFloats[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
negativeFloats[ndx] = -positiveFloats[ndx];
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"%fname = OpString \"negateInputs.comp\"\n"
"OpSource GLSL 430\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpModuleProcessed \"VULKAN CTS\"\n" //OpModuleProcessed;
"OpModuleProcessed \"Negative values\"\n"
"OpModuleProcessed \"Date: 2017/09/21\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
+ string(getComputeAsmInputOutputBufferTraits())
+ string(getComputeAsmCommonTypes()) + string(getComputeAsmInputOutputBuffer()) +
"OpLine %fname 0 1\n"
"OpLine %fname 1000 1\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc = OpAccessChain %f32ptr %indata %zero %x\n"
"%inval = OpLoad %f32 %inloc\n"
"%neg = OpFNegate %f32 %inval\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
" OpStore %outloc %neg\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(positiveFloats)));
spec.outputs.push_back(BufferSp(new Float32Buffer(negativeFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.verifyBinary = veryfiBinaryShader;
spec.spirvVersion = SPIRV_VERSION_1_3;
group->addChild(new SpvAsmComputeShaderCase(testCtx, "all", "OpModuleProcessed Tests", spec));
return group.release();
}
tcu::TestCaseGroup* createOpNoLineGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opnoline", "Test the OpNoLine instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 100;
vector<float> positiveFloats (numElements, 0);
vector<float> negativeFloats (numElements, 0);
fillRandomScalars(rnd, 1.f, 100.f, &positiveFloats[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
negativeFloats[ndx] = -positiveFloats[ndx];
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"%fname = OpString \"negateInputs.comp\"\n"
"OpSource GLSL 430\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
+ string(getComputeAsmInputOutputBufferTraits()) +
"OpNoLine\n" // At the earliest possible position, without preceding OpLine
+ string(getComputeAsmCommonTypes()) + string(getComputeAsmInputOutputBuffer()) +
"OpLine %fname 0 1\n"
"OpNoLine\n" // Immediately following a preceding OpLine
"OpLine %fname 1000 1\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"OpNoLine\n" // Contents after the previous OpLine
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"OpNoLine\n" // Multiple OpNoLine
"OpNoLine\n"
"OpNoLine\n"
"%inloc = OpAccessChain %f32ptr %indata %zero %x\n"
"%inval = OpLoad %f32 %inloc\n"
"%neg = OpFNegate %f32 %inval\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
" OpStore %outloc %neg\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(positiveFloats)));
spec.outputs.push_back(BufferSp(new Float32Buffer(negativeFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "all", "OpNoLine appearing at different places", spec));
return group.release();
}
// Compare instruction for the contraction compute case.
// Returns true if the output is what is expected from the test case.
bool compareNoContractCase(const std::vector<Resource>&, const vector<AllocationSp>& outputAllocs, const std::vector<Resource>& expectedOutputs, TestLog&)
{
if (outputAllocs.size() != 1)
return false;
// Only size is needed because we are not comparing the exact values.
size_t byteSize = expectedOutputs[0].getByteSize();
const float* outputAsFloat = static_cast<const float*>(outputAllocs[0]->getHostPtr());
for(size_t i = 0; i < byteSize / sizeof(float); ++i) {
if (outputAsFloat[i] != 0.f &&
outputAsFloat[i] != -ldexp(1, -24)) {
return false;
}
}
return true;
}
tcu::TestCaseGroup* createNoContractionGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "nocontraction", "Test the NoContraction decoration"));
vector<CaseParameter> cases;
const int numElements = 100;
vector<float> inputFloats1 (numElements, 0);
vector<float> inputFloats2 (numElements, 0);
vector<float> outputFloats (numElements, 0);
const StringTemplate shaderTemplate (
string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"${DECORATION}\n"
"OpDecorate %buf BufferBlock\n"
"OpDecorate %indata1 DescriptorSet 0\n"
"OpDecorate %indata1 Binding 0\n"
"OpDecorate %indata2 DescriptorSet 0\n"
"OpDecorate %indata2 Binding 1\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 2\n"
"OpDecorate %f32arr ArrayStride 4\n"
"OpMemberDecorate %buf 0 Offset 0\n"
+ string(getComputeAsmCommonTypes()) +
"%buf = OpTypeStruct %f32arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata1 = OpVariable %bufptr Uniform\n"
"%indata2 = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%c_f_m1 = OpConstant %f32 -1.\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc1 = OpAccessChain %f32ptr %indata1 %zero %x\n"
"%inval1 = OpLoad %f32 %inloc1\n"
"%inloc2 = OpAccessChain %f32ptr %indata2 %zero %x\n"
"%inval2 = OpLoad %f32 %inloc2\n"
"%mul = OpFMul %f32 %inval1 %inval2\n"
"%add = OpFAdd %f32 %mul %c_f_m1\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
" OpStore %outloc %add\n"
" OpReturn\n"
" OpFunctionEnd\n");
cases.push_back(CaseParameter("multiplication", "OpDecorate %mul NoContraction"));
cases.push_back(CaseParameter("addition", "OpDecorate %add NoContraction"));
cases.push_back(CaseParameter("both", "OpDecorate %mul NoContraction\nOpDecorate %add NoContraction"));
for (size_t ndx = 0; ndx < numElements; ++ndx)
{
inputFloats1[ndx] = 1.f + std::ldexp(1.f, -23); // 1 + 2^-23.
inputFloats2[ndx] = 1.f - std::ldexp(1.f, -23); // 1 - 2^-23.
// Result for (1 + 2^-23) * (1 - 2^-23) - 1. With NoContraction, the multiplication will be
// conducted separately and the result is rounded to 1, or 0x1.fffffcp-1
// So the final result will be 0.f or 0x1p-24.
// If the operation is combined into a precise fused multiply-add, then the result would be
// 2^-46 (0xa8800000).
outputFloats[ndx] = 0.f;
}
for (size_t caseNdx = 0; caseNdx < cases.size(); ++caseNdx)
{
map<string, string> specializations;
ComputeShaderSpec spec;
specializations["DECORATION"] = cases[caseNdx].param;
spec.assembly = shaderTemplate.specialize(specializations);
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats1)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats2)));
spec.outputs.push_back(BufferSp(new Float32Buffer(outputFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
// Check against the two possible answers based on rounding mode.
spec.verifyIO = &compareNoContractCase;
group->addChild(new SpvAsmComputeShaderCase(testCtx, cases[caseNdx].name, cases[caseNdx].name, spec));
}
return group.release();
}
bool compareFRem(const std::vector<Resource>&, const vector<AllocationSp>& outputAllocs, const std::vector<Resource>& expectedOutputs, TestLog&)
{
if (outputAllocs.size() != 1)
return false;
vector<deUint8> expectedBytes;
expectedOutputs[0].getBytes(expectedBytes);
const float* expectedOutputAsFloat = reinterpret_cast<const float*>(&expectedBytes.front());
const float* outputAsFloat = static_cast<const float*>(outputAllocs[0]->getHostPtr());
for (size_t idx = 0; idx < expectedBytes.size() / sizeof(float); ++idx)
{
const float f0 = expectedOutputAsFloat[idx];
const float f1 = outputAsFloat[idx];
// \todo relative error needs to be fairly high because FRem may be implemented as
// (roughly) frac(a/b)*b, so LSB errors can be magnified. But this should be fine for now.
if (deFloatAbs((f1 - f0) / f0) > 0.02)
return false;
}
return true;
}
tcu::TestCaseGroup* createOpFRemGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opfrem", "Test the OpFRem instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 200;
vector<float> inputFloats1 (numElements, 0);
vector<float> inputFloats2 (numElements, 0);
vector<float> outputFloats (numElements, 0);
fillRandomScalars(rnd, -10000.f, 10000.f, &inputFloats1[0], numElements);
fillRandomScalars(rnd, -100.f, 100.f, &inputFloats2[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
{
// Guard against divisors near zero.
if (std::fabs(inputFloats2[ndx]) < 1e-3)
inputFloats2[ndx] = 8.f;
// The return value of std::fmod() has the same sign as its first operand, which is how OpFRem spec'd.
outputFloats[ndx] = std::fmod(inputFloats1[ndx], inputFloats2[ndx]);
}
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %buf BufferBlock\n"
"OpDecorate %indata1 DescriptorSet 0\n"
"OpDecorate %indata1 Binding 0\n"
"OpDecorate %indata2 DescriptorSet 0\n"
"OpDecorate %indata2 Binding 1\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 2\n"
"OpDecorate %f32arr ArrayStride 4\n"
"OpMemberDecorate %buf 0 Offset 0\n"
+ string(getComputeAsmCommonTypes()) +
"%buf = OpTypeStruct %f32arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata1 = OpVariable %bufptr Uniform\n"
"%indata2 = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc1 = OpAccessChain %f32ptr %indata1 %zero %x\n"
"%inval1 = OpLoad %f32 %inloc1\n"
"%inloc2 = OpAccessChain %f32ptr %indata2 %zero %x\n"
"%inval2 = OpLoad %f32 %inloc2\n"
"%rem = OpFRem %f32 %inval1 %inval2\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
" OpStore %outloc %rem\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats1)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats2)));
spec.outputs.push_back(BufferSp(new Float32Buffer(outputFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.verifyIO = &compareFRem;
group->addChild(new SpvAsmComputeShaderCase(testCtx, "all", "", spec));
return group.release();
}
bool compareNMin (const std::vector<Resource>&, const vector<AllocationSp>& outputAllocs, const std::vector<Resource>& expectedOutputs, TestLog&)
{
if (outputAllocs.size() != 1)
return false;
const BufferSp& expectedOutput (expectedOutputs[0].getBuffer());
std::vector<deUint8> data;
expectedOutput->getBytes(data);
const float* const expectedOutputAsFloat = reinterpret_cast<const float*>(&data.front());
const float* const outputAsFloat = static_cast<const float*>(outputAllocs[0]->getHostPtr());
for (size_t idx = 0; idx < expectedOutput->getByteSize() / sizeof(float); ++idx)
{
const float f0 = expectedOutputAsFloat[idx];
const float f1 = outputAsFloat[idx];
// For NMin, we accept NaN as output if both inputs were NaN.
// Otherwise the NaN is the wrong choise, as on architectures that
// do not handle NaN, those are huge values.
if (!(tcu::Float32(f1).isNaN() && tcu::Float32(f0).isNaN()) && deFloatAbs(f1 - f0) > 0.00001f)
return false;
}
return true;
}
tcu::TestCaseGroup* createOpNMinGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opnmin", "Test the OpNMin instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 200;
vector<float> inputFloats1 (numElements, 0);
vector<float> inputFloats2 (numElements, 0);
vector<float> outputFloats (numElements, 0);
fillRandomScalars(rnd, -10000.f, 10000.f, &inputFloats1[0], numElements);
fillRandomScalars(rnd, -10000.f, 10000.f, &inputFloats2[0], numElements);
// Make the first case a full-NAN case.
inputFloats1[0] = TCU_NAN;
inputFloats2[0] = TCU_NAN;
for (size_t ndx = 0; ndx < numElements; ++ndx)
{
// By default, pick the smallest
outputFloats[ndx] = std::min(inputFloats1[ndx], inputFloats2[ndx]);
// Make half of the cases NaN cases
if ((ndx & 1) == 0)
{
// Alternate between the NaN operand
if ((ndx & 2) == 0)
{
outputFloats[ndx] = inputFloats2[ndx];
inputFloats1[ndx] = TCU_NAN;
}
else
{
outputFloats[ndx] = inputFloats1[ndx];
inputFloats2[ndx] = TCU_NAN;
}
}
}
spec.assembly =
"OpCapability Shader\n"
"%std450 = OpExtInstImport \"GLSL.std.450\"\n"
"OpMemoryModel Logical GLSL450\n"
"OpEntryPoint GLCompute %main \"main\" %id\n"
"OpExecutionMode %main LocalSize 1 1 1\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %buf BufferBlock\n"
"OpDecorate %indata1 DescriptorSet 0\n"
"OpDecorate %indata1 Binding 0\n"
"OpDecorate %indata2 DescriptorSet 0\n"
"OpDecorate %indata2 Binding 1\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 2\n"
"OpDecorate %f32arr ArrayStride 4\n"
"OpMemberDecorate %buf 0 Offset 0\n"
+ string(getComputeAsmCommonTypes()) +
"%buf = OpTypeStruct %f32arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata1 = OpVariable %bufptr Uniform\n"
"%indata2 = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc1 = OpAccessChain %f32ptr %indata1 %zero %x\n"
"%inval1 = OpLoad %f32 %inloc1\n"
"%inloc2 = OpAccessChain %f32ptr %indata2 %zero %x\n"
"%inval2 = OpLoad %f32 %inloc2\n"
"%rem = OpExtInst %f32 %std450 NMin %inval1 %inval2\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
" OpStore %outloc %rem\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats1)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats2)));
spec.outputs.push_back(BufferSp(new Float32Buffer(outputFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.verifyIO = &compareNMin;
group->addChild(new SpvAsmComputeShaderCase(testCtx, "all", "", spec));
return group.release();
}
bool compareNMax (const std::vector<Resource>&, const vector<AllocationSp>& outputAllocs, const std::vector<Resource>& expectedOutputs, TestLog&)
{
if (outputAllocs.size() != 1)
return false;
const BufferSp& expectedOutput = expectedOutputs[0].getBuffer();
std::vector<deUint8> data;
expectedOutput->getBytes(data);
const float* const expectedOutputAsFloat = reinterpret_cast<const float*>(&data.front());
const float* const outputAsFloat = static_cast<const float*>(outputAllocs[0]->getHostPtr());
for (size_t idx = 0; idx < expectedOutput->getByteSize() / sizeof(float); ++idx)
{
const float f0 = expectedOutputAsFloat[idx];
const float f1 = outputAsFloat[idx];
// For NMax, NaN is considered acceptable result, since in
// architectures that do not handle NaNs, those are huge values.
if (!tcu::Float32(f1).isNaN() && deFloatAbs(f1 - f0) > 0.00001f)
return false;
}
return true;
}
tcu::TestCaseGroup* createOpNMaxGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group(new tcu::TestCaseGroup(testCtx, "opnmax", "Test the OpNMax instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 200;
vector<float> inputFloats1 (numElements, 0);
vector<float> inputFloats2 (numElements, 0);
vector<float> outputFloats (numElements, 0);
fillRandomScalars(rnd, -10000.f, 10000.f, &inputFloats1[0], numElements);
fillRandomScalars(rnd, -10000.f, 10000.f, &inputFloats2[0], numElements);
// Make the first case a full-NAN case.
inputFloats1[0] = TCU_NAN;
inputFloats2[0] = TCU_NAN;
for (size_t ndx = 0; ndx < numElements; ++ndx)
{
// By default, pick the biggest
outputFloats[ndx] = std::max(inputFloats1[ndx], inputFloats2[ndx]);
// Make half of the cases NaN cases
if ((ndx & 1) == 0)
{
// Alternate between the NaN operand
if ((ndx & 2) == 0)
{
outputFloats[ndx] = inputFloats2[ndx];
inputFloats1[ndx] = TCU_NAN;
}
else
{
outputFloats[ndx] = inputFloats1[ndx];
inputFloats2[ndx] = TCU_NAN;
}
}
}
spec.assembly =
"OpCapability Shader\n"
"%std450 = OpExtInstImport \"GLSL.std.450\"\n"
"OpMemoryModel Logical GLSL450\n"
"OpEntryPoint GLCompute %main \"main\" %id\n"
"OpExecutionMode %main LocalSize 1 1 1\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %buf BufferBlock\n"
"OpDecorate %indata1 DescriptorSet 0\n"
"OpDecorate %indata1 Binding 0\n"
"OpDecorate %indata2 DescriptorSet 0\n"
"OpDecorate %indata2 Binding 1\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 2\n"
"OpDecorate %f32arr ArrayStride 4\n"
"OpMemberDecorate %buf 0 Offset 0\n"
+ string(getComputeAsmCommonTypes()) +
"%buf = OpTypeStruct %f32arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata1 = OpVariable %bufptr Uniform\n"
"%indata2 = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc1 = OpAccessChain %f32ptr %indata1 %zero %x\n"
"%inval1 = OpLoad %f32 %inloc1\n"
"%inloc2 = OpAccessChain %f32ptr %indata2 %zero %x\n"
"%inval2 = OpLoad %f32 %inloc2\n"
"%rem = OpExtInst %f32 %std450 NMax %inval1 %inval2\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
" OpStore %outloc %rem\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats1)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats2)));
spec.outputs.push_back(BufferSp(new Float32Buffer(outputFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.verifyIO = &compareNMax;
group->addChild(new SpvAsmComputeShaderCase(testCtx, "all", "", spec));
return group.release();
}
bool compareNClamp (const std::vector<Resource>&, const vector<AllocationSp>& outputAllocs, const std::vector<Resource>& expectedOutputs, TestLog&)
{
if (outputAllocs.size() != 1)
return false;
const BufferSp& expectedOutput = expectedOutputs[0].getBuffer();
std::vector<deUint8> data;
expectedOutput->getBytes(data);
const float* const expectedOutputAsFloat = reinterpret_cast<const float*>(&data.front());
const float* const outputAsFloat = static_cast<const float*>(outputAllocs[0]->getHostPtr());
for (size_t idx = 0; idx < expectedOutput->getByteSize() / sizeof(float) / 2; ++idx)
{
const float e0 = expectedOutputAsFloat[idx * 2];
const float e1 = expectedOutputAsFloat[idx * 2 + 1];
const float res = outputAsFloat[idx];
// For NClamp, we have two possible outcomes based on
// whether NaNs are handled or not.
// If either min or max value is NaN, the result is undefined,
// so this test doesn't stress those. If the clamped value is
// NaN, and NaNs are handled, the result is min; if NaNs are not
// handled, they are big values that result in max.
// If all three parameters are NaN, the result should be NaN.
if (!((tcu::Float32(e0).isNaN() && tcu::Float32(res).isNaN()) ||
(deFloatAbs(e0 - res) < 0.00001f) ||
(deFloatAbs(e1 - res) < 0.00001f)))
return false;
}
return true;
}
tcu::TestCaseGroup* createOpNClampGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opnclamp", "Test the OpNClamp instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 200;
vector<float> inputFloats1 (numElements, 0);
vector<float> inputFloats2 (numElements, 0);
vector<float> inputFloats3 (numElements, 0);
vector<float> outputFloats (numElements * 2, 0);
fillRandomScalars(rnd, -10000.f, 10000.f, &inputFloats1[0], numElements);
fillRandomScalars(rnd, -10000.f, 10000.f, &inputFloats2[0], numElements);
fillRandomScalars(rnd, -10000.f, 10000.f, &inputFloats3[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
{
// Results are only defined if max value is bigger than min value.
if (inputFloats2[ndx] > inputFloats3[ndx])
{
float t = inputFloats2[ndx];
inputFloats2[ndx] = inputFloats3[ndx];
inputFloats3[ndx] = t;
}
// By default, do the clamp, setting both possible answers
float defaultRes = std::min(std::max(inputFloats1[ndx], inputFloats2[ndx]), inputFloats3[ndx]);
float maxResA = std::max(inputFloats1[ndx], inputFloats2[ndx]);
float maxResB = maxResA;
// Alternate between the NaN cases
if (ndx & 1)
{
inputFloats1[ndx] = TCU_NAN;
// If NaN is handled, the result should be same as the clamp minimum.
// If NaN is not handled, the result should clamp to the clamp maximum.
maxResA = inputFloats2[ndx];
maxResB = inputFloats3[ndx];
}
else
{
// Not a NaN case - only one legal result.
maxResA = defaultRes;
maxResB = defaultRes;
}
outputFloats[ndx * 2] = maxResA;
outputFloats[ndx * 2 + 1] = maxResB;
}
// Make the first case a full-NAN case.
inputFloats1[0] = TCU_NAN;
inputFloats2[0] = TCU_NAN;
inputFloats3[0] = TCU_NAN;
outputFloats[0] = TCU_NAN;
outputFloats[1] = TCU_NAN;
spec.assembly =
"OpCapability Shader\n"
"%std450 = OpExtInstImport \"GLSL.std.450\"\n"
"OpMemoryModel Logical GLSL450\n"
"OpEntryPoint GLCompute %main \"main\" %id\n"
"OpExecutionMode %main LocalSize 1 1 1\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %buf BufferBlock\n"
"OpDecorate %indata1 DescriptorSet 0\n"
"OpDecorate %indata1 Binding 0\n"
"OpDecorate %indata2 DescriptorSet 0\n"
"OpDecorate %indata2 Binding 1\n"
"OpDecorate %indata3 DescriptorSet 0\n"
"OpDecorate %indata3 Binding 2\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 3\n"
"OpDecorate %f32arr ArrayStride 4\n"
"OpMemberDecorate %buf 0 Offset 0\n"
+ string(getComputeAsmCommonTypes()) +
"%buf = OpTypeStruct %f32arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata1 = OpVariable %bufptr Uniform\n"
"%indata2 = OpVariable %bufptr Uniform\n"
"%indata3 = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc1 = OpAccessChain %f32ptr %indata1 %zero %x\n"
"%inval1 = OpLoad %f32 %inloc1\n"
"%inloc2 = OpAccessChain %f32ptr %indata2 %zero %x\n"
"%inval2 = OpLoad %f32 %inloc2\n"
"%inloc3 = OpAccessChain %f32ptr %indata3 %zero %x\n"
"%inval3 = OpLoad %f32 %inloc3\n"
"%rem = OpExtInst %f32 %std450 NClamp %inval1 %inval2 %inval3\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
" OpStore %outloc %rem\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats1)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats2)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats3)));
spec.outputs.push_back(BufferSp(new Float32Buffer(outputFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.verifyIO = &compareNClamp;
group->addChild(new SpvAsmComputeShaderCase(testCtx, "all", "", spec));
return group.release();
}
tcu::TestCaseGroup* createOpSRemComputeGroup (tcu::TestContext& testCtx, qpTestResult negFailResult)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opsrem", "Test the OpSRem instruction"));
de::Random rnd (deStringHash(group->getName()));
const int numElements = 200;
const struct CaseParams
{
const char* name;
const char* failMessage; // customized status message
qpTestResult failResult; // override status on failure
int op1Min, op1Max; // operand ranges
int op2Min, op2Max;
} cases[] =
{
{ "positive", "Output doesn't match with expected", QP_TEST_RESULT_FAIL, 0, 65536, 0, 100 },
{ "all", "Inconsistent results, but within specification", negFailResult, -65536, 65536, -100, 100 }, // see below
};
// If either operand is negative the result is undefined. Some implementations may still return correct values.
for (int caseNdx = 0; caseNdx < DE_LENGTH_OF_ARRAY(cases); ++caseNdx)
{
const CaseParams& params = cases[caseNdx];
ComputeShaderSpec spec;
vector<deInt32> inputInts1 (numElements, 0);
vector<deInt32> inputInts2 (numElements, 0);
vector<deInt32> outputInts (numElements, 0);
fillRandomScalars(rnd, params.op1Min, params.op1Max, &inputInts1[0], numElements);
fillRandomScalars(rnd, params.op2Min, params.op2Max, &inputInts2[0], numElements, filterNotZero);
for (int ndx = 0; ndx < numElements; ++ndx)
{
// The return value of std::fmod() has the same sign as its first operand, which is how OpFRem spec'd.
outputInts[ndx] = inputInts1[ndx] % inputInts2[ndx];
}
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %buf BufferBlock\n"
"OpDecorate %indata1 DescriptorSet 0\n"
"OpDecorate %indata1 Binding 0\n"
"OpDecorate %indata2 DescriptorSet 0\n"
"OpDecorate %indata2 Binding 1\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 2\n"
"OpDecorate %i32arr ArrayStride 4\n"
"OpMemberDecorate %buf 0 Offset 0\n"
+ string(getComputeAsmCommonTypes()) +
"%buf = OpTypeStruct %i32arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata1 = OpVariable %bufptr Uniform\n"
"%indata2 = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc1 = OpAccessChain %i32ptr %indata1 %zero %x\n"
"%inval1 = OpLoad %i32 %inloc1\n"
"%inloc2 = OpAccessChain %i32ptr %indata2 %zero %x\n"
"%inval2 = OpLoad %i32 %inloc2\n"
"%rem = OpSRem %i32 %inval1 %inval2\n"
"%outloc = OpAccessChain %i32ptr %outdata %zero %x\n"
" OpStore %outloc %rem\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back (BufferSp(new Int32Buffer(inputInts1)));
spec.inputs.push_back (BufferSp(new Int32Buffer(inputInts2)));
spec.outputs.push_back (BufferSp(new Int32Buffer(outputInts)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.failResult = params.failResult;
spec.failMessage = params.failMessage;
group->addChild(new SpvAsmComputeShaderCase(testCtx, params.name, "", spec));
}
return group.release();
}
tcu::TestCaseGroup* createOpSRemComputeGroup64 (tcu::TestContext& testCtx, qpTestResult negFailResult)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opsrem64", "Test the 64-bit OpSRem instruction"));
de::Random rnd (deStringHash(group->getName()));
const int numElements = 200;
const struct CaseParams
{
const char* name;
const char* failMessage; // customized status message
qpTestResult failResult; // override status on failure
bool positive;
} cases[] =
{
{ "positive", "Output doesn't match with expected", QP_TEST_RESULT_FAIL, true },
{ "all", "Inconsistent results, but within specification", negFailResult, false }, // see below
};
// If either operand is negative the result is undefined. Some implementations may still return correct values.
for (int caseNdx = 0; caseNdx < DE_LENGTH_OF_ARRAY(cases); ++caseNdx)
{
const CaseParams& params = cases[caseNdx];
ComputeShaderSpec spec;
vector<deInt64> inputInts1 (numElements, 0);
vector<deInt64> inputInts2 (numElements, 0);
vector<deInt64> outputInts (numElements, 0);
if (params.positive)
{
fillRandomInt64sLogDistributed(rnd, inputInts1, numElements, filterNonNegative);
fillRandomInt64sLogDistributed(rnd, inputInts2, numElements, filterPositive);
}
else
{
fillRandomInt64sLogDistributed(rnd, inputInts1, numElements);
fillRandomInt64sLogDistributed(rnd, inputInts2, numElements, filterNotZero);
}
for (int ndx = 0; ndx < numElements; ++ndx)
{
// The return value of std::fmod() has the same sign as its first operand, which is how OpFRem spec'd.
outputInts[ndx] = inputInts1[ndx] % inputInts2[ndx];
}
spec.assembly =
"OpCapability Int64\n"
+ string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %buf BufferBlock\n"
"OpDecorate %indata1 DescriptorSet 0\n"
"OpDecorate %indata1 Binding 0\n"
"OpDecorate %indata2 DescriptorSet 0\n"
"OpDecorate %indata2 Binding 1\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 2\n"
"OpDecorate %i64arr ArrayStride 8\n"
"OpMemberDecorate %buf 0 Offset 0\n"
+ string(getComputeAsmCommonTypes())
+ string(getComputeAsmCommonInt64Types()) +
"%buf = OpTypeStruct %i64arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata1 = OpVariable %bufptr Uniform\n"
"%indata2 = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i64 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc1 = OpAccessChain %i64ptr %indata1 %zero %x\n"
"%inval1 = OpLoad %i64 %inloc1\n"
"%inloc2 = OpAccessChain %i64ptr %indata2 %zero %x\n"
"%inval2 = OpLoad %i64 %inloc2\n"
"%rem = OpSRem %i64 %inval1 %inval2\n"
"%outloc = OpAccessChain %i64ptr %outdata %zero %x\n"
" OpStore %outloc %rem\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back (BufferSp(new Int64Buffer(inputInts1)));
spec.inputs.push_back (BufferSp(new Int64Buffer(inputInts2)));
spec.outputs.push_back (BufferSp(new Int64Buffer(outputInts)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.failResult = params.failResult;
spec.failMessage = params.failMessage;
spec.requestedVulkanFeatures.coreFeatures.shaderInt64 = VK_TRUE;
group->addChild(new SpvAsmComputeShaderCase(testCtx, params.name, "", spec));
}
return group.release();
}
tcu::TestCaseGroup* createOpSModComputeGroup (tcu::TestContext& testCtx, qpTestResult negFailResult)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opsmod", "Test the OpSMod instruction"));
de::Random rnd (deStringHash(group->getName()));
const int numElements = 200;
const struct CaseParams
{
const char* name;
const char* failMessage; // customized status message
qpTestResult failResult; // override status on failure
int op1Min, op1Max; // operand ranges
int op2Min, op2Max;
} cases[] =
{
{ "positive", "Output doesn't match with expected", QP_TEST_RESULT_FAIL, 0, 65536, 0, 100 },
{ "all", "Inconsistent results, but within specification", negFailResult, -65536, 65536, -100, 100 }, // see below
};
// If either operand is negative the result is undefined. Some implementations may still return correct values.
for (int caseNdx = 0; caseNdx < DE_LENGTH_OF_ARRAY(cases); ++caseNdx)
{
const CaseParams& params = cases[caseNdx];
ComputeShaderSpec spec;
vector<deInt32> inputInts1 (numElements, 0);
vector<deInt32> inputInts2 (numElements, 0);
vector<deInt32> outputInts (numElements, 0);
fillRandomScalars(rnd, params.op1Min, params.op1Max, &inputInts1[0], numElements);
fillRandomScalars(rnd, params.op2Min, params.op2Max, &inputInts2[0], numElements, filterNotZero);
for (int ndx = 0; ndx < numElements; ++ndx)
{
deInt32 rem = inputInts1[ndx] % inputInts2[ndx];
if (rem == 0)
{
outputInts[ndx] = 0;
}
else if ((inputInts1[ndx] >= 0) == (inputInts2[ndx] >= 0))
{
// They have the same sign
outputInts[ndx] = rem;
}
else
{
// They have opposite sign. The remainder operation takes the
// sign inputInts1[ndx] but OpSMod is supposed to take ths sign
// of inputInts2[ndx]. Adding inputInts2[ndx] will ensure that
// the result has the correct sign and that it is still
// congruent to inputInts1[ndx] modulo inputInts2[ndx]
//
// See also http://mathforum.org/library/drmath/view/52343.html
outputInts[ndx] = rem + inputInts2[ndx];
}
}
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %buf BufferBlock\n"
"OpDecorate %indata1 DescriptorSet 0\n"
"OpDecorate %indata1 Binding 0\n"
"OpDecorate %indata2 DescriptorSet 0\n"
"OpDecorate %indata2 Binding 1\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 2\n"
"OpDecorate %i32arr ArrayStride 4\n"
"OpMemberDecorate %buf 0 Offset 0\n"
+ string(getComputeAsmCommonTypes()) +
"%buf = OpTypeStruct %i32arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata1 = OpVariable %bufptr Uniform\n"
"%indata2 = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc1 = OpAccessChain %i32ptr %indata1 %zero %x\n"
"%inval1 = OpLoad %i32 %inloc1\n"
"%inloc2 = OpAccessChain %i32ptr %indata2 %zero %x\n"
"%inval2 = OpLoad %i32 %inloc2\n"
"%rem = OpSMod %i32 %inval1 %inval2\n"
"%outloc = OpAccessChain %i32ptr %outdata %zero %x\n"
" OpStore %outloc %rem\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back (BufferSp(new Int32Buffer(inputInts1)));
spec.inputs.push_back (BufferSp(new Int32Buffer(inputInts2)));
spec.outputs.push_back (BufferSp(new Int32Buffer(outputInts)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.failResult = params.failResult;
spec.failMessage = params.failMessage;
group->addChild(new SpvAsmComputeShaderCase(testCtx, params.name, "", spec));
}
return group.release();
}
tcu::TestCaseGroup* createOpSModComputeGroup64 (tcu::TestContext& testCtx, qpTestResult negFailResult)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opsmod64", "Test the OpSMod instruction"));
de::Random rnd (deStringHash(group->getName()));
const int numElements = 200;
const struct CaseParams
{
const char* name;
const char* failMessage; // customized status message
qpTestResult failResult; // override status on failure
bool positive;
} cases[] =
{
{ "positive", "Output doesn't match with expected", QP_TEST_RESULT_FAIL, true },
{ "all", "Inconsistent results, but within specification", negFailResult, false }, // see below
};
// If either operand is negative the result is undefined. Some implementations may still return correct values.
for (int caseNdx = 0; caseNdx < DE_LENGTH_OF_ARRAY(cases); ++caseNdx)
{
const CaseParams& params = cases[caseNdx];
ComputeShaderSpec spec;
vector<deInt64> inputInts1 (numElements, 0);
vector<deInt64> inputInts2 (numElements, 0);
vector<deInt64> outputInts (numElements, 0);
if (params.positive)
{
fillRandomInt64sLogDistributed(rnd, inputInts1, numElements, filterNonNegative);
fillRandomInt64sLogDistributed(rnd, inputInts2, numElements, filterPositive);
}
else
{
fillRandomInt64sLogDistributed(rnd, inputInts1, numElements);
fillRandomInt64sLogDistributed(rnd, inputInts2, numElements, filterNotZero);
}
for (int ndx = 0; ndx < numElements; ++ndx)
{
deInt64 rem = inputInts1[ndx] % inputInts2[ndx];
if (rem == 0)
{
outputInts[ndx] = 0;
}
else if ((inputInts1[ndx] >= 0) == (inputInts2[ndx] >= 0))
{
// They have the same sign
outputInts[ndx] = rem;
}
else
{
// They have opposite sign. The remainder operation takes the
// sign inputInts1[ndx] but OpSMod is supposed to take ths sign
// of inputInts2[ndx]. Adding inputInts2[ndx] will ensure that
// the result has the correct sign and that it is still
// congruent to inputInts1[ndx] modulo inputInts2[ndx]
//
// See also http://mathforum.org/library/drmath/view/52343.html
outputInts[ndx] = rem + inputInts2[ndx];
}
}
spec.assembly =
"OpCapability Int64\n"
+ string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %buf BufferBlock\n"
"OpDecorate %indata1 DescriptorSet 0\n"
"OpDecorate %indata1 Binding 0\n"
"OpDecorate %indata2 DescriptorSet 0\n"
"OpDecorate %indata2 Binding 1\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 2\n"
"OpDecorate %i64arr ArrayStride 8\n"
"OpMemberDecorate %buf 0 Offset 0\n"
+ string(getComputeAsmCommonTypes())
+ string(getComputeAsmCommonInt64Types()) +
"%buf = OpTypeStruct %i64arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata1 = OpVariable %bufptr Uniform\n"
"%indata2 = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i64 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc1 = OpAccessChain %i64ptr %indata1 %zero %x\n"
"%inval1 = OpLoad %i64 %inloc1\n"
"%inloc2 = OpAccessChain %i64ptr %indata2 %zero %x\n"
"%inval2 = OpLoad %i64 %inloc2\n"
"%rem = OpSMod %i64 %inval1 %inval2\n"
"%outloc = OpAccessChain %i64ptr %outdata %zero %x\n"
" OpStore %outloc %rem\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back (BufferSp(new Int64Buffer(inputInts1)));
spec.inputs.push_back (BufferSp(new Int64Buffer(inputInts2)));
spec.outputs.push_back (BufferSp(new Int64Buffer(outputInts)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.failResult = params.failResult;
spec.failMessage = params.failMessage;
spec.requestedVulkanFeatures.coreFeatures.shaderInt64 = VK_TRUE;
group->addChild(new SpvAsmComputeShaderCase(testCtx, params.name, "", spec));
}
return group.release();
}
// Copy contents in the input buffer to the output buffer.
tcu::TestCaseGroup* createOpCopyMemoryGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opcopymemory", "Test the OpCopyMemory instruction"));
de::Random rnd (deStringHash(group->getName()));
const int numElements = 100;
// The following case adds vec4(0., 0.5, 1.5, 2.5) to each of the elements in the input buffer and writes output to the output buffer.
ComputeShaderSpec spec1;
vector<Vec4> inputFloats1 (numElements);
vector<Vec4> outputFloats1 (numElements);
fillRandomScalars(rnd, -200.f, 200.f, &inputFloats1[0], numElements * 4);
// CPU might not use the same rounding mode as the GPU. Use whole numbers to avoid rounding differences.
floorAll(inputFloats1);
for (size_t ndx = 0; ndx < numElements; ++ndx)
outputFloats1[ndx] = inputFloats1[ndx] + Vec4(0.f, 0.5f, 1.5f, 2.5f);
spec1.assembly =
string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %vec4arr ArrayStride 16\n"
+ string(getComputeAsmInputOutputBufferTraits()) + string(getComputeAsmCommonTypes()) +
"%vec4 = OpTypeVector %f32 4\n"
"%vec4ptr_u = OpTypePointer Uniform %vec4\n"
"%vec4ptr_f = OpTypePointer Function %vec4\n"
"%vec4arr = OpTypeRuntimeArray %vec4\n"
"%buf = OpTypeStruct %vec4arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%c_f_0 = OpConstant %f32 0.\n"
"%c_f_0_5 = OpConstant %f32 0.5\n"
"%c_f_1_5 = OpConstant %f32 1.5\n"
"%c_f_2_5 = OpConstant %f32 2.5\n"
"%c_vec4 = OpConstantComposite %vec4 %c_f_0 %c_f_0_5 %c_f_1_5 %c_f_2_5\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%v_vec4 = OpVariable %vec4ptr_f Function\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc = OpAccessChain %vec4ptr_u %indata %zero %x\n"
"%outloc = OpAccessChain %vec4ptr_u %outdata %zero %x\n"
" OpCopyMemory %v_vec4 %inloc\n"
"%v_vec4_val = OpLoad %vec4 %v_vec4\n"
"%add = OpFAdd %vec4 %v_vec4_val %c_vec4\n"
" OpStore %outloc %add\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec1.inputs.push_back(BufferSp(new Vec4Buffer(inputFloats1)));
spec1.outputs.push_back(BufferSp(new Vec4Buffer(outputFloats1)));
spec1.numWorkGroups = IVec3(numElements, 1, 1);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "vector", "OpCopyMemory elements of vector type", spec1));
// The following case copies a float[100] variable from the input buffer to the output buffer.
ComputeShaderSpec spec2;
vector<float> inputFloats2 (numElements);
vector<float> outputFloats2 (numElements);
fillRandomScalars(rnd, -200.f, 200.f, &inputFloats2[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
outputFloats2[ndx] = inputFloats2[ndx];
spec2.assembly =
string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %f32arr100 ArrayStride 4\n"
+ string(getComputeAsmInputOutputBufferTraits()) + string(getComputeAsmCommonTypes()) +
"%hundred = OpConstant %u32 100\n"
"%f32arr100 = OpTypeArray %f32 %hundred\n"
"%f32arr100ptr_f = OpTypePointer Function %f32arr100\n"
"%f32arr100ptr_u = OpTypePointer Uniform %f32arr100\n"
"%buf = OpTypeStruct %f32arr100\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%var = OpVariable %f32arr100ptr_f Function\n"
"%inarr = OpAccessChain %f32arr100ptr_u %indata %zero\n"
"%outarr = OpAccessChain %f32arr100ptr_u %outdata %zero\n"
" OpCopyMemory %var %inarr\n"
" OpCopyMemory %outarr %var\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec2.inputs.push_back(BufferSp(new Float32Buffer(inputFloats2)));
spec2.outputs.push_back(BufferSp(new Float32Buffer(outputFloats2)));
spec2.numWorkGroups = IVec3(1, 1, 1);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "array", "OpCopyMemory elements of array type", spec2));
// The following case copies a struct{vec4, vec4, vec4, vec4} variable from the input buffer to the output buffer.
ComputeShaderSpec spec3;
vector<float> inputFloats3 (16);
vector<float> outputFloats3 (16);
fillRandomScalars(rnd, -200.f, 200.f, &inputFloats3[0], 16);
for (size_t ndx = 0; ndx < 16; ++ndx)
outputFloats3[ndx] = inputFloats3[ndx];
spec3.assembly =
string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
//"OpMemberDecorate %buf 0 Offset 0\n" - exists in getComputeAsmInputOutputBufferTraits
"OpMemberDecorate %buf 1 Offset 16\n"
"OpMemberDecorate %buf 2 Offset 32\n"
"OpMemberDecorate %buf 3 Offset 48\n"
+ string(getComputeAsmInputOutputBufferTraits()) + string(getComputeAsmCommonTypes()) +
"%vec4 = OpTypeVector %f32 4\n"
"%buf = OpTypeStruct %vec4 %vec4 %vec4 %vec4\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%vec4stptr = OpTypePointer Function %buf\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%var = OpVariable %vec4stptr Function\n"
" OpCopyMemory %var %indata\n"
" OpCopyMemory %outdata %var\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec3.inputs.push_back(BufferSp(new Float32Buffer(inputFloats3)));
spec3.outputs.push_back(BufferSp(new Float32Buffer(outputFloats3)));
spec3.numWorkGroups = IVec3(1, 1, 1);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "struct", "OpCopyMemory elements of struct type", spec3));
// The following case negates multiple float variables from the input buffer and stores the results to the output buffer.
ComputeShaderSpec spec4;
vector<float> inputFloats4 (numElements);
vector<float> outputFloats4 (numElements);
fillRandomScalars(rnd, -200.f, 200.f, &inputFloats4[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
outputFloats4[ndx] = -inputFloats4[ndx];
spec4.assembly =
string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
+ string(getComputeAsmInputOutputBufferTraits()) + string(getComputeAsmCommonTypes()) + string(getComputeAsmInputOutputBuffer()) +
"%f32ptr_f = OpTypePointer Function %f32\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%var = OpVariable %f32ptr_f Function\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc = OpAccessChain %f32ptr %indata %zero %x\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
" OpCopyMemory %var %inloc\n"
"%val = OpLoad %f32 %var\n"
"%neg = OpFNegate %f32 %val\n"
" OpStore %outloc %neg\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec4.inputs.push_back(BufferSp(new Float32Buffer(inputFloats4)));
spec4.outputs.push_back(BufferSp(new Float32Buffer(outputFloats4)));
spec4.numWorkGroups = IVec3(numElements, 1, 1);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "float", "OpCopyMemory elements of float type", spec4));
return group.release();
}
tcu::TestCaseGroup* createOpCopyObjectGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opcopyobject", "Test the OpCopyObject instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 100;
vector<float> inputFloats (numElements, 0);
vector<float> outputFloats (numElements, 0);
fillRandomScalars(rnd, -200.f, 200.f, &inputFloats[0], numElements);
// CPU might not use the same rounding mode as the GPU. Use whole numbers to avoid rounding differences.
floorAll(inputFloats);
for (size_t ndx = 0; ndx < numElements; ++ndx)
outputFloats[ndx] = inputFloats[ndx] + 7.5f;
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
+ string(getComputeAsmInputOutputBufferTraits()) + string(getComputeAsmCommonTypes()) +
"%fmat = OpTypeMatrix %fvec3 3\n"
"%three = OpConstant %u32 3\n"
"%farr = OpTypeArray %f32 %three\n"
"%fst = OpTypeStruct %f32 %f32\n"
+ string(getComputeAsmInputOutputBuffer()) +
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%c_f = OpConstant %f32 1.5\n"
"%c_fvec3 = OpConstantComposite %fvec3 %c_f %c_f %c_f\n"
"%c_fmat = OpConstantComposite %fmat %c_fvec3 %c_fvec3 %c_fvec3\n"
"%c_farr = OpConstantComposite %farr %c_f %c_f %c_f\n"
"%c_fst = OpConstantComposite %fst %c_f %c_f\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%c_f_copy = OpCopyObject %f32 %c_f\n"
"%c_fvec3_copy = OpCopyObject %fvec3 %c_fvec3\n"
"%c_fmat_copy = OpCopyObject %fmat %c_fmat\n"
"%c_farr_copy = OpCopyObject %farr %c_farr\n"
"%c_fst_copy = OpCopyObject %fst %c_fst\n"
"%fvec3_elem = OpCompositeExtract %f32 %c_fvec3_copy 0\n"
"%fmat_elem = OpCompositeExtract %f32 %c_fmat_copy 1 2\n"
"%farr_elem = OpCompositeExtract %f32 %c_farr_copy 2\n"
"%fst_elem = OpCompositeExtract %f32 %c_fst_copy 1\n"
// Add up. 1.5 * 5 = 7.5.
"%add1 = OpFAdd %f32 %c_f_copy %fvec3_elem\n"
"%add2 = OpFAdd %f32 %add1 %fmat_elem\n"
"%add3 = OpFAdd %f32 %add2 %farr_elem\n"
"%add4 = OpFAdd %f32 %add3 %fst_elem\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc = OpAccessChain %f32ptr %indata %zero %x\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
"%inval = OpLoad %f32 %inloc\n"
"%add = OpFAdd %f32 %add4 %inval\n"
" OpStore %outloc %add\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats)));
spec.outputs.push_back(BufferSp(new Float32Buffer(outputFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "spotcheck", "OpCopyObject on different types", spec));
return group.release();
}
// Assembly code used for testing OpUnreachable is based on GLSL source code:
//
// #version 430
//
// layout(std140, set = 0, binding = 0) readonly buffer Input {
// float elements[];
// } input_data;
// layout(std140, set = 0, binding = 1) writeonly buffer Output {
// float elements[];
// } output_data;
//
// void not_called_func() {
// // place OpUnreachable here
// }
//
// uint modulo4(uint val) {
// switch (val % uint(4)) {
// case 0: return 3;
// case 1: return 2;
// case 2: return 1;
// case 3: return 0;
// default: return 100; // place OpUnreachable here
// }
// }
//
// uint const5() {
// return 5;
// // place OpUnreachable here
// }
//
// void main() {
// uint x = gl_GlobalInvocationID.x;
// if (const5() > modulo4(1000)) {
// output_data.elements[x] = -input_data.elements[x];
// } else {
// // place OpUnreachable here
// output_data.elements[x] = input_data.elements[x];
// }
// }
tcu::TestCaseGroup* createOpUnreachableGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opunreachable", "Test the OpUnreachable instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 100;
vector<float> positiveFloats (numElements, 0);
vector<float> negativeFloats (numElements, 0);
fillRandomScalars(rnd, 1.f, 100.f, &positiveFloats[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
negativeFloats[ndx] = -positiveFloats[ndx];
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"OpSource GLSL 430\n"
"OpName %main \"main\"\n"
"OpName %func_not_called_func \"not_called_func(\"\n"
"OpName %func_modulo4 \"modulo4(u1;\"\n"
"OpName %func_const5 \"const5(\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
+ string(getComputeAsmInputOutputBufferTraits()) + string(getComputeAsmCommonTypes()) +
"%u32ptr = OpTypePointer Function %u32\n"
"%uintfuint = OpTypeFunction %u32 %u32ptr\n"
"%unitf = OpTypeFunction %u32\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %u32 0\n"
"%one = OpConstant %u32 1\n"
"%two = OpConstant %u32 2\n"
"%three = OpConstant %u32 3\n"
"%four = OpConstant %u32 4\n"
"%five = OpConstant %u32 5\n"
"%hundred = OpConstant %u32 100\n"
"%thousand = OpConstant %u32 1000\n"
+ string(getComputeAsmInputOutputBuffer()) +
// Main()
"%main = OpFunction %void None %voidf\n"
"%main_entry = OpLabel\n"
"%v_thousand = OpVariable %u32ptr Function %thousand\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc = OpAccessChain %f32ptr %indata %zero %x\n"
"%inval = OpLoad %f32 %inloc\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
"%ret_const5 = OpFunctionCall %u32 %func_const5\n"
"%ret_modulo4 = OpFunctionCall %u32 %func_modulo4 %v_thousand\n"
"%cmp_gt = OpUGreaterThan %bool %ret_const5 %ret_modulo4\n"
" OpSelectionMerge %if_end None\n"
" OpBranchConditional %cmp_gt %if_true %if_false\n"
"%if_true = OpLabel\n"
"%negate = OpFNegate %f32 %inval\n"
" OpStore %outloc %negate\n"
" OpBranch %if_end\n"
"%if_false = OpLabel\n"
" OpUnreachable\n" // Unreachable else branch for if statement
"%if_end = OpLabel\n"
" OpReturn\n"
" OpFunctionEnd\n"
// not_called_function()
"%func_not_called_func = OpFunction %void None %voidf\n"
"%not_called_func_entry = OpLabel\n"
" OpUnreachable\n" // Unreachable entry block in not called static function
" OpFunctionEnd\n"
// modulo4()
"%func_modulo4 = OpFunction %u32 None %uintfuint\n"
"%valptr = OpFunctionParameter %u32ptr\n"
"%modulo4_entry = OpLabel\n"
"%val = OpLoad %u32 %valptr\n"
"%modulo = OpUMod %u32 %val %four\n"
" OpSelectionMerge %switch_merge None\n"
" OpSwitch %modulo %default 0 %case0 1 %case1 2 %case2 3 %case3\n"
"%case0 = OpLabel\n"
" OpReturnValue %three\n"
"%case1 = OpLabel\n"
" OpReturnValue %two\n"
"%case2 = OpLabel\n"
" OpReturnValue %one\n"
"%case3 = OpLabel\n"
" OpReturnValue %zero\n"
"%default = OpLabel\n"
" OpUnreachable\n" // Unreachable default case for switch statement
"%switch_merge = OpLabel\n"
" OpUnreachable\n" // Unreachable merge block for switch statement
" OpFunctionEnd\n"
// const5()
"%func_const5 = OpFunction %u32 None %unitf\n"
"%const5_entry = OpLabel\n"
" OpReturnValue %five\n"
"%unreachable = OpLabel\n"
" OpUnreachable\n" // Unreachable block in function
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(positiveFloats)));
spec.outputs.push_back(BufferSp(new Float32Buffer(negativeFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "all", "OpUnreachable appearing at different places", spec));
return group.release();
}
// Assembly code used for testing decoration group is based on GLSL source code:
//
// #version 430
//
// layout(std140, set = 0, binding = 0) readonly buffer Input0 {
// float elements[];
// } input_data0;
// layout(std140, set = 0, binding = 1) readonly buffer Input1 {
// float elements[];
// } input_data1;
// layout(std140, set = 0, binding = 2) readonly buffer Input2 {
// float elements[];
// } input_data2;
// layout(std140, set = 0, binding = 3) readonly buffer Input3 {
// float elements[];
// } input_data3;
// layout(std140, set = 0, binding = 4) readonly buffer Input4 {
// float elements[];
// } input_data4;
// layout(std140, set = 0, binding = 5) writeonly buffer Output {
// float elements[];
// } output_data;
//
// void main() {
// uint x = gl_GlobalInvocationID.x;
// output_data.elements[x] = input_data0.elements[x] + input_data1.elements[x] + input_data2.elements[x] + input_data3.elements[x] + input_data4.elements[x];
// }
tcu::TestCaseGroup* createDecorationGroupGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "decoration_group", "Test the OpDecorationGroup & OpGroupDecorate instruction"));
ComputeShaderSpec spec;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 100;
vector<float> inputFloats0 (numElements, 0);
vector<float> inputFloats1 (numElements, 0);
vector<float> inputFloats2 (numElements, 0);
vector<float> inputFloats3 (numElements, 0);
vector<float> inputFloats4 (numElements, 0);
vector<float> outputFloats (numElements, 0);
fillRandomScalars(rnd, -300.f, 300.f, &inputFloats0[0], numElements);
fillRandomScalars(rnd, -300.f, 300.f, &inputFloats1[0], numElements);
fillRandomScalars(rnd, -300.f, 300.f, &inputFloats2[0], numElements);
fillRandomScalars(rnd, -300.f, 300.f, &inputFloats3[0], numElements);
fillRandomScalars(rnd, -300.f, 300.f, &inputFloats4[0], numElements);
// CPU might not use the same rounding mode as the GPU. Use whole numbers to avoid rounding differences.
floorAll(inputFloats0);
floorAll(inputFloats1);
floorAll(inputFloats2);
floorAll(inputFloats3);
floorAll(inputFloats4);
for (size_t ndx = 0; ndx < numElements; ++ndx)
outputFloats[ndx] = inputFloats0[ndx] + inputFloats1[ndx] + inputFloats2[ndx] + inputFloats3[ndx] + inputFloats4[ndx];
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"OpSource GLSL 430\n"
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
// Not using group decoration on variable.
"OpDecorate %id BuiltIn GlobalInvocationId\n"
// Not using group decoration on type.
"OpDecorate %f32arr ArrayStride 4\n"
"OpDecorate %groups BufferBlock\n"
"OpDecorate %groupm Offset 0\n"
"%groups = OpDecorationGroup\n"
"%groupm = OpDecorationGroup\n"
// Group decoration on multiple structs.
"OpGroupDecorate %groups %outbuf %inbuf0 %inbuf1 %inbuf2 %inbuf3 %inbuf4\n"
// Group decoration on multiple struct members.
"OpGroupMemberDecorate %groupm %outbuf 0 %inbuf0 0 %inbuf1 0 %inbuf2 0 %inbuf3 0 %inbuf4 0\n"
"OpDecorate %group1 DescriptorSet 0\n"
"OpDecorate %group3 DescriptorSet 0\n"
"OpDecorate %group3 NonWritable\n"
"OpDecorate %group3 Restrict\n"
"%group0 = OpDecorationGroup\n"
"%group1 = OpDecorationGroup\n"
"%group3 = OpDecorationGroup\n"
// Applying the same decoration group multiple times.
"OpGroupDecorate %group1 %outdata\n"
"OpGroupDecorate %group1 %outdata\n"
"OpGroupDecorate %group1 %outdata\n"
"OpDecorate %outdata DescriptorSet 0\n"
"OpDecorate %outdata Binding 5\n"
// Applying decoration group containing nothing.
"OpGroupDecorate %group0 %indata0\n"
"OpDecorate %indata0 DescriptorSet 0\n"
"OpDecorate %indata0 Binding 0\n"
// Applying decoration group containing one decoration.
"OpGroupDecorate %group1 %indata1\n"
"OpDecorate %indata1 Binding 1\n"
// Applying decoration group containing multiple decorations.
"OpGroupDecorate %group3 %indata2 %indata3\n"
"OpDecorate %indata2 Binding 2\n"
"OpDecorate %indata3 Binding 3\n"
// Applying multiple decoration groups (with overlapping).
"OpGroupDecorate %group0 %indata4\n"
"OpGroupDecorate %group1 %indata4\n"
"OpGroupDecorate %group3 %indata4\n"
"OpDecorate %indata4 Binding 4\n"
+ string(getComputeAsmCommonTypes()) +
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%outbuf = OpTypeStruct %f32arr\n"
"%outbufptr = OpTypePointer Uniform %outbuf\n"
"%outdata = OpVariable %outbufptr Uniform\n"
"%inbuf0 = OpTypeStruct %f32arr\n"
"%inbuf0ptr = OpTypePointer Uniform %inbuf0\n"
"%indata0 = OpVariable %inbuf0ptr Uniform\n"
"%inbuf1 = OpTypeStruct %f32arr\n"
"%inbuf1ptr = OpTypePointer Uniform %inbuf1\n"
"%indata1 = OpVariable %inbuf1ptr Uniform\n"
"%inbuf2 = OpTypeStruct %f32arr\n"
"%inbuf2ptr = OpTypePointer Uniform %inbuf2\n"
"%indata2 = OpVariable %inbuf2ptr Uniform\n"
"%inbuf3 = OpTypeStruct %f32arr\n"
"%inbuf3ptr = OpTypePointer Uniform %inbuf3\n"
"%indata3 = OpVariable %inbuf3ptr Uniform\n"
"%inbuf4 = OpTypeStruct %f32arr\n"
"%inbufptr = OpTypePointer Uniform %inbuf4\n"
"%indata4 = OpVariable %inbufptr Uniform\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc0 = OpAccessChain %f32ptr %indata0 %zero %x\n"
"%inloc1 = OpAccessChain %f32ptr %indata1 %zero %x\n"
"%inloc2 = OpAccessChain %f32ptr %indata2 %zero %x\n"
"%inloc3 = OpAccessChain %f32ptr %indata3 %zero %x\n"
"%inloc4 = OpAccessChain %f32ptr %indata4 %zero %x\n"
"%outloc = OpAccessChain %f32ptr %outdata %zero %x\n"
"%inval0 = OpLoad %f32 %inloc0\n"
"%inval1 = OpLoad %f32 %inloc1\n"
"%inval2 = OpLoad %f32 %inloc2\n"
"%inval3 = OpLoad %f32 %inloc3\n"
"%inval4 = OpLoad %f32 %inloc4\n"
"%add0 = OpFAdd %f32 %inval0 %inval1\n"
"%add1 = OpFAdd %f32 %add0 %inval2\n"
"%add2 = OpFAdd %f32 %add1 %inval3\n"
"%add = OpFAdd %f32 %add2 %inval4\n"
" OpStore %outloc %add\n"
" OpReturn\n"
" OpFunctionEnd\n";
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats0)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats1)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats2)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats3)));
spec.inputs.push_back(BufferSp(new Float32Buffer(inputFloats4)));
spec.outputs.push_back(BufferSp(new Float32Buffer(outputFloats)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
group->addChild(new SpvAsmComputeShaderCase(testCtx, "all", "decoration group cases", spec));
return group.release();
}
struct SpecConstantTwoIntCase
{
const char* caseName;
const char* scDefinition0;
const char* scDefinition1;
const char* scResultType;
const char* scOperation;
deInt32 scActualValue0;
deInt32 scActualValue1;
const char* resultOperation;
vector<deInt32> expectedOutput;
deInt32 scActualValueLength;
SpecConstantTwoIntCase (const char* name,
const char* definition0,
const char* definition1,
const char* resultType,
const char* operation,
deInt32 value0,
deInt32 value1,
const char* resultOp,
const vector<deInt32>& output,
const deInt32 valueLength = sizeof(deInt32))
: caseName (name)
, scDefinition0 (definition0)
, scDefinition1 (definition1)
, scResultType (resultType)
, scOperation (operation)
, scActualValue0 (value0)
, scActualValue1 (value1)
, resultOperation (resultOp)
, expectedOutput (output)
, scActualValueLength (valueLength)
{}
};
tcu::TestCaseGroup* createSpecConstantGroup (tcu::TestContext& testCtx)
{
de::MovePtr<tcu::TestCaseGroup> group (new tcu::TestCaseGroup(testCtx, "opspecconstantop", "Test the OpSpecConstantOp instruction"));
vector<SpecConstantTwoIntCase> cases;
de::Random rnd (deStringHash(group->getName()));
const int numElements = 100;
const deInt32 p1AsFloat16 = 0x3c00; // +1(fp16) == 0 01111 0000000000 == 0011 1100 0000 0000
vector<deInt32> inputInts (numElements, 0);
vector<deInt32> outputInts1 (numElements, 0);
vector<deInt32> outputInts2 (numElements, 0);
vector<deInt32> outputInts3 (numElements, 0);
vector<deInt32> outputInts4 (numElements, 0);
const StringTemplate shaderTemplate (
"${CAPABILITIES:opt}"
+ string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %sc_0 SpecId 0\n"
"OpDecorate %sc_1 SpecId 1\n"
"OpDecorate %i32arr ArrayStride 4\n"
+ string(getComputeAsmInputOutputBufferTraits()) + string(getComputeAsmCommonTypes()) +
"${OPTYPE_DEFINITIONS:opt}"
"%buf = OpTypeStruct %i32arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%sc_0 = OpSpecConstant${SC_DEF0}\n"
"%sc_1 = OpSpecConstant${SC_DEF1}\n"
"%sc_final = OpSpecConstantOp ${SC_RESULT_TYPE} ${SC_OP}\n"
"%main = OpFunction %void None %voidf\n"
"%label = OpLabel\n"
"${TYPE_CONVERT:opt}"
"%idval = OpLoad %uvec3 %id\n"
"%x = OpCompositeExtract %u32 %idval 0\n"
"%inloc = OpAccessChain %i32ptr %indata %zero %x\n"
"%inval = OpLoad %i32 %inloc\n"
"%final = ${GEN_RESULT}\n"
"%outloc = OpAccessChain %i32ptr %outdata %zero %x\n"
" OpStore %outloc %final\n"
" OpReturn\n"
" OpFunctionEnd\n");
fillRandomScalars(rnd, -65536, 65536, &inputInts[0], numElements);
for (size_t ndx = 0; ndx < numElements; ++ndx)
{
outputInts1[ndx] = inputInts[ndx] + 42;
outputInts2[ndx] = inputInts[ndx];
outputInts3[ndx] = inputInts[ndx] - 11200;
outputInts4[ndx] = inputInts[ndx] + 1;
}
const char addScToInput[] = "OpIAdd %i32 %inval %sc_final";
const char addSc32ToInput[] = "OpIAdd %i32 %inval %sc_final32";
const char selectTrueUsingSc[] = "OpSelect %i32 %sc_final %inval %zero";
const char selectFalseUsingSc[] = "OpSelect %i32 %sc_final %zero %inval";
cases.push_back(SpecConstantTwoIntCase("iadd", " %i32 0", " %i32 0", "%i32", "IAdd %sc_0 %sc_1", 62, -20, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("isub", " %i32 0", " %i32 0", "%i32", "ISub %sc_0 %sc_1", 100, 58, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("imul", " %i32 0", " %i32 0", "%i32", "IMul %sc_0 %sc_1", -2, -21, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("sdiv", " %i32 0", " %i32 0", "%i32", "SDiv %sc_0 %sc_1", -126, -3, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("udiv", " %i32 0", " %i32 0", "%i32", "UDiv %sc_0 %sc_1", 126, 3, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("srem", " %i32 0", " %i32 0", "%i32", "SRem %sc_0 %sc_1", 7, 3, addScToInput, outputInts4));
cases.push_back(SpecConstantTwoIntCase("smod", " %i32 0", " %i32 0", "%i32", "SMod %sc_0 %sc_1", 7, 3, addScToInput, outputInts4));
cases.push_back(SpecConstantTwoIntCase("umod", " %i32 0", " %i32 0", "%i32", "UMod %sc_0 %sc_1", 342, 50, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("bitwiseand", " %i32 0", " %i32 0", "%i32", "BitwiseAnd %sc_0 %sc_1", 42, 63, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("bitwiseor", " %i32 0", " %i32 0", "%i32", "BitwiseOr %sc_0 %sc_1", 34, 8, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("bitwisexor", " %i32 0", " %i32 0", "%i32", "BitwiseXor %sc_0 %sc_1", 18, 56, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("shiftrightlogical", " %i32 0", " %i32 0", "%i32", "ShiftRightLogical %sc_0 %sc_1", 168, 2, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("shiftrightarithmetic", " %i32 0", " %i32 0", "%i32", "ShiftRightArithmetic %sc_0 %sc_1", 168, 2, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("shiftleftlogical", " %i32 0", " %i32 0", "%i32", "ShiftLeftLogical %sc_0 %sc_1", 21, 1, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("slessthan", " %i32 0", " %i32 0", "%bool", "SLessThan %sc_0 %sc_1", -20, -10, selectTrueUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("ulessthan", " %i32 0", " %i32 0", "%bool", "ULessThan %sc_0 %sc_1", 10, 20, selectTrueUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("sgreaterthan", " %i32 0", " %i32 0", "%bool", "SGreaterThan %sc_0 %sc_1", -1000, 50, selectFalseUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("ugreaterthan", " %i32 0", " %i32 0", "%bool", "UGreaterThan %sc_0 %sc_1", 10, 5, selectTrueUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("slessthanequal", " %i32 0", " %i32 0", "%bool", "SLessThanEqual %sc_0 %sc_1", -10, -10, selectTrueUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("ulessthanequal", " %i32 0", " %i32 0", "%bool", "ULessThanEqual %sc_0 %sc_1", 50, 100, selectTrueUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("sgreaterthanequal", " %i32 0", " %i32 0", "%bool", "SGreaterThanEqual %sc_0 %sc_1", -1000, 50, selectFalseUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("ugreaterthanequal", " %i32 0", " %i32 0", "%bool", "UGreaterThanEqual %sc_0 %sc_1", 10, 10, selectTrueUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("iequal", " %i32 0", " %i32 0", "%bool", "IEqual %sc_0 %sc_1", 42, 24, selectFalseUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("inotequal", " %i32 0", " %i32 0", "%bool", "INotEqual %sc_0 %sc_1", 42, 24, selectTrueUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("logicaland", "True %bool", "True %bool", "%bool", "LogicalAnd %sc_0 %sc_1", 0, 1, selectFalseUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("logicalor", "False %bool", "False %bool", "%bool", "LogicalOr %sc_0 %sc_1", 1, 0, selectTrueUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("logicalequal", "True %bool", "True %bool", "%bool", "LogicalEqual %sc_0 %sc_1", 0, 1, selectFalseUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("logicalnotequal", "False %bool", "False %bool", "%bool", "LogicalNotEqual %sc_0 %sc_1", 1, 0, selectTrueUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("snegate", " %i32 0", " %i32 0", "%i32", "SNegate %sc_0", -42, 0, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("not", " %i32 0", " %i32 0", "%i32", "Not %sc_0", -43, 0, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("logicalnot", "False %bool", "False %bool", "%bool", "LogicalNot %sc_0", 1, 0, selectFalseUsingSc, outputInts2));
cases.push_back(SpecConstantTwoIntCase("select", "False %bool", " %i32 0", "%i32", "Select %sc_0 %sc_1 %zero", 1, 42, addScToInput, outputInts1));
cases.push_back(SpecConstantTwoIntCase("sconvert", " %i32 0", " %i32 0", "%i16", "SConvert %sc_0", -11200, 0, addSc32ToInput, outputInts3));
// -969998336 stored as 32-bit two's complement is the binary representation of -11200 as IEEE-754 Float
cases.push_back(SpecConstantTwoIntCase("fconvert", " %f32 0", " %f32 0", "%f64", "FConvert %sc_0", -969998336, 0, addSc32ToInput, outputInts3));
cases.push_back(SpecConstantTwoIntCase("fconvert16", " %f16 0", " %f16 0", "%f32", "FConvert %sc_0", p1AsFloat16, 0, addSc32ToInput, outputInts4, sizeof(deFloat16)));
for (size_t caseNdx = 0; caseNdx < cases.size(); ++caseNdx)
{
map<string, string> specializations;
ComputeShaderSpec spec;
specializations["SC_DEF0"] = cases[caseNdx].scDefinition0;
specializations["SC_DEF1"] = cases[caseNdx].scDefinition1;
specializations["SC_RESULT_TYPE"] = cases[caseNdx].scResultType;
specializations["SC_OP"] = cases[caseNdx].scOperation;
specializations["GEN_RESULT"] = cases[caseNdx].resultOperation;
// Special SPIR-V code for SConvert-case
if (strcmp(cases[caseNdx].caseName, "sconvert") == 0)
{
spec.requestedVulkanFeatures.coreFeatures.shaderInt16 = VK_TRUE;
specializations["CAPABILITIES"] = "OpCapability Int16\n"; // Adds 16-bit integer capability
specializations["OPTYPE_DEFINITIONS"] = "%i16 = OpTypeInt 16 1\n"; // Adds 16-bit integer type
specializations["TYPE_CONVERT"] = "%sc_final32 = OpSConvert %i32 %sc_final\n"; // Converts 16-bit integer to 32-bit integer
}
// Special SPIR-V code for FConvert-case
if (strcmp(cases[caseNdx].caseName, "fconvert") == 0)
{
spec.requestedVulkanFeatures.coreFeatures.shaderFloat64 = VK_TRUE;
specializations["CAPABILITIES"] = "OpCapability Float64\n"; // Adds 64-bit float capability
specializations["OPTYPE_DEFINITIONS"] = "%f64 = OpTypeFloat 64\n"; // Adds 64-bit float type
specializations["TYPE_CONVERT"] = "%sc_final32 = OpConvertFToS %i32 %sc_final\n"; // Converts 64-bit float to 32-bit integer
}
// Special SPIR-V code for FConvert-case for 16-bit floats
if (strcmp(cases[caseNdx].caseName, "fconvert16") == 0)
{
spec.extensions.push_back("VK_KHR_shader_float16_int8");
spec.requestedVulkanFeatures.extFloat16Int8 = EXTFLOAT16INT8FEATURES_FLOAT16;
specializations["CAPABILITIES"] = "OpCapability Float16\n"; // Adds 16-bit float capability
specializations["OPTYPE_DEFINITIONS"] = "%f16 = OpTypeFloat 16\n"; // Adds 16-bit float type
specializations["TYPE_CONVERT"] = "%sc_final32 = OpConvertFToS %i32 %sc_final\n"; // Converts 16-bit float to 32-bit integer
}
spec.assembly = shaderTemplate.specialize(specializations);
spec.inputs.push_back(BufferSp(new Int32Buffer(inputInts)));
spec.outputs.push_back(BufferSp(new Int32Buffer(cases[caseNdx].expectedOutput)));
spec.numWorkGroups = IVec3(numElements, 1, 1);
spec.specConstants.append(&cases[caseNdx].scActualValue0, cases[caseNdx].scActualValueLength);
spec.specConstants.append(&cases[caseNdx].scActualValue1, cases[caseNdx].scActualValueLength);
group->addChild(new SpvAsmComputeShaderCase(testCtx, cases[caseNdx].caseName, cases[caseNdx].caseName, spec));
}
ComputeShaderSpec spec;
spec.assembly =
string(getComputeAsmShaderPreamble()) +
"OpName %main \"main\"\n"
"OpName %id \"gl_GlobalInvocationID\"\n"
"OpDecorate %id BuiltIn GlobalInvocationId\n"
"OpDecorate %sc_0 SpecId 0\n"
"OpDecorate %sc_1 SpecId 1\n"
"OpDecorate %sc_2 SpecId 2\n"
"OpDecorate %i32arr ArrayStride 4\n"
+ string(getComputeAsmInputOutputBufferTraits()) + string(getComputeAsmCommonTypes()) +
"%ivec3 = OpTypeVector %i32 3\n"
"%buf = OpTypeStruct %i32arr\n"
"%bufptr = OpTypePointer Uniform %buf\n"
"%indata = OpVariable %bufptr Uniform\n"
"%outdata = OpVariable %bufptr Uniform\n"
"%id = OpVariable %uvec3ptr Input\n"
"%zero = OpConstant %i32 0\n"
"%ivec3_0 = OpConstantComposite %ivec3 %zero %zero %zero\n"
"%vec3_undef = OpUndef %ivec3\n"
"%sc_0 = OpSpecConstant %i32 0\n"
"%sc_1 = OpSpecConstant %i32 0\n"
"%sc_2 = OpSpecConstant %i32 0\n"
"%sc_vec3_0 = OpSpecConstantOp %ivec3 CompositeInsert %sc_0 %ivec3_0 0\n" // (sc_0, 0, 0)
"%sc_vec3_1 = OpSpecConstantOp %ivec3 CompositeInsert %sc_1 %ivec3_0 1\n" // (0, sc_1, 0)
"%sc_vec3_2 = OpSpecConstantOp %ivec3 CompositeInsert %sc_2 %ivec3_0 2\n" // (0, 0, sc_2)
"%sc_vec3_0_s = OpSpecConstantOp %ivec3 VectorShuffle %sc_vec3_0 %vec3_undef 0 0xFFFFFFFF 2\n" // (sc_0, ???, 0)
"%sc_vec3_1_s = OpSpecConstantOp %ivec3 VectorShuffle %sc_vec3_1 %vec3_undef 0xFFFFFFFF 1 0\n" // (???, sc_1, 0)
"%sc_vec3_2_s = OpSpecConstantOp %ivec3 VectorShuffle %vec3_undef %sc_vec3_2 5 0xFFFFFFFF 5\n" // (sc_2, ???, sc_2)
"%sc_vec3_01 = OpSpecConstantOp %ivec3 VectorShuffle %sc_vec3_0_s %sc_vec3_1_s 1 0 4\n" // (0, sc_0, sc_1)
"%sc_vec3_012 = OpSpecConstantOp %ivec3 VectorShuffle %sc_vec3_01 %sc_vec3_2_s 5 1 2\n"