Merge remote-tracking branch 'origin/swift-4.2-branch' into stable
diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
index 6e8ff3a..58a2c63 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -4842,6 +4842,13 @@
return MachineOutlinerInstrType::Illegal;
}
+ // Make sure none of the operands are un-outlinable.
+ for (const MachineOperand &MOP : MI.operands()) {
+ if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
+ MOP.isTargetIndex())
+ return MachineOutlinerInstrType::Illegal;
+ }
+
// Special cases for instructions that can always be outlined, but will fail
// the later tests. e.g, ADRPs, which are PC-relative use LR, but can always
// be outlined because they don't require a *specific* value to be in LR.
@@ -4921,17 +4928,6 @@
MI.modifiesRegister(AArch64::W30, &getRegisterInfo()))
return MachineOutlinerInstrType::Illegal;
- // Make sure none of the operands are un-outlinable.
- for (const MachineOperand &MOP : MI.operands()) {
- if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
- MOP.isTargetIndex())
- return MachineOutlinerInstrType::Illegal;
-
- // Don't outline anything that uses the link register.
- if (MOP.isReg() && getRegisterInfo().regsOverlap(MOP.getReg(), AArch64::LR))
- return MachineOutlinerInstrType::Illegal;
- }
-
// Does this use the stack?
if (MI.modifiesRegister(AArch64::SP, &RI) ||
MI.readsRegister(AArch64::SP, &RI)) {
diff --git a/test/CodeGen/AArch64/machine-outliner-bad-adrp.mir b/test/CodeGen/AArch64/machine-outliner-bad-adrp.mir
new file mode 100644
index 0000000..721e91a
--- /dev/null
+++ b/test/CodeGen/AArch64/machine-outliner-bad-adrp.mir
@@ -0,0 +1,41 @@
+
+# RUN: llc -mtriple=aarch64--- -verify-machineinstrs -simplify-mir -run-pass=machine-outliner %s -o - | FileCheck %s
+--- |
+
+ define void @foo() #0 {
+ ret void
+ }
+
+ attributes #0 = { noredzone}
+...
+---
+name: foo
+constants:
+ - id: 0
+ value: 'float 1.990000e+02'
+ alignment: 4
+ isTargetSpecific: false
+body: |
+ bb.0:
+ liveins: %w1, %w10, %x14, %x15, %x16, %x10, %lr
+ ; CHECK-NOT: BL
+
+ %w10 = MOVZWi 4, 0, implicit-def %x10
+
+ renamable %x14 = ADRP target-flags(aarch64-page) %const.0
+ renamable %x15 = ADRP target-flags(aarch64-page) %const.0
+ renamable %x16 = ADRP target-flags(aarch64-page) %const.0
+
+ %w10 = MOVZWi 5, 0, implicit-def %x10
+
+ renamable %x14 = ADRP target-flags(aarch64-page) %const.0
+ renamable %x15 = ADRP target-flags(aarch64-page) %const.0
+ renamable %x16 = ADRP target-flags(aarch64-page) %const.0
+
+ %w10 = MOVZWi 6, 0, implicit-def %x10
+
+ renamable %x14 = ADRP target-flags(aarch64-page) %const.0
+ renamable %x15 = ADRP target-flags(aarch64-page) %const.0
+ renamable %x16 = ADRP target-flags(aarch64-page) %const.0
+
+ RET undef %lr
\ No newline at end of file
