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fuchsia / third_party / rust / 1aa01927d3b8eeec06db1cd72e23b08983aa3104
commit1aa01927d3b8eeec06db1cd72e23b08983aa3104[log] [tgz]
author许杰友 Jieyou Xu (Joe) <39484203+jieyouxu@users.noreply.github.com>Sat Nov 30 12:57:32 2024 +0800
committerGitHub <noreply@github.com>Sat Nov 30 12:57:32 2024 +0800
treea0bfe91315b9e8d7d0ce9cb8ce2613b76b18aad2
parent76f3ff605962d7046bc1537597ceed5e12325f54 [diff]
parentdf8feb5067f99e20059c7ee8021d9ba5273bfe68 [diff]
Rollup merge of #131551 - taiki-e:ppc-asm-vreg-inout, r=Amanieu

Support input/output in vector registers of PowerPC inline assembly

This extends currently clobber-only vector registers (`vreg`) support to allow passing `#[repr(simd)]` types as input/output.

| Architecture | Register class | Target feature | Allowed types |
| ------------ | -------------- | -------------- | -------------- |
| PowerPC      | `vreg` | `altivec` | `i8x16`, `i16x8`, `i32x4`, `f32x4` |
| PowerPC      | `vreg` | `vsx` | `f32`, `f64`, `i64x2`, `f64x2` |

In addition to floats and `core::simd` types listed above, `core::arch` types and custom `#[repr(simd)]` types of the same size and type are also allowed. All allowed types and relevant target features are currently unstable.

r? `@Amanieu`

`@rustbot` label +O-PowerPC +A-inline-assembly
tree: a0bfe91315b9e8d7d0ce9cb8ce2613b76b18aad2
  1. .github/
  2. compiler/
  3. library/
  4. LICENSES/
  5. src/
  6. tests/
  7. .clang-format
  8. .editorconfig
  9. .git-blame-ignore-revs
  10. .gitattributes
  11. .gitignore
  12. .gitmodules
  13. .ignore
  14. .mailmap
  15. Cargo.lock
  16. Cargo.toml
  17. CODE_OF_CONDUCT.md
  18. config.example.toml
  19. configure
  20. CONTRIBUTING.md
  21. COPYRIGHT
  22. INSTALL.md
  23. LICENSE-APACHE
  24. license-metadata.json
  25. LICENSE-MIT
  26. README.md
  27. RELEASES.md
  28. REUSE.toml
  29. rust-bors.toml
  30. rustfmt.toml
  31. triagebot.toml
  32. x
  33. x.ps1
  34. x.py
README.md

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