[intel-hda] Fix some W1C bits in the stream control/status register.
The IRQ pending bits in the stream status register (BCIS, FIFOE, DESE)
have write-one-clear behavior regardless of if they are accesses with
a single byte write to the Status register, or a 32-bit word write to
the Control/Status register. Update the register definition so that
the word access works properly as well.
See sections 3.3.36 and 4.5.6 of the Intel High Definition Audio
Specification Rev 1.0a dated June 17, 2010
Change-Id: I6bc4515029edc09cad2ff75143c7f7e593c5ca2d
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
index 948268a..6aa9097 100644
--- a/hw/audio/intel-hda.c
+++ b/hw/audio/intel-hda.c
@@ -812,6 +812,7 @@
.name = _t stringify(_i) " CTL", \
.size = 4, \
.wmask = 0x1cff001f, \
+ .wclear = 0x1c000000, \
.offset = offsetof(IntelHDAState, st[_i].ctl), \
.whandler = intel_hda_set_st_ctl, \
}, \
