| # |
| # RISC-V translation routines for the RVXI Base Integer Instruction Set. |
| # |
| # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de |
| # Bastian Koppelmann, kbastian@mail.uni-paderborn.de |
| # |
| # This program is free software; you can redistribute it and/or modify it |
| # under the terms and conditions of the GNU General Public License, |
| # version 2 or later, as published by the Free Software Foundation. |
| # |
| # This program is distributed in the hope it will be useful, but WITHOUT |
| # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| # more details. |
| # |
| # You should have received a copy of the GNU General Public License along with |
| # this program. If not, see <http://www.gnu.org/licenses/>. |
| |
| # Fields: |
| %rs3 27:5 |
| %rs2 20:5 |
| %rs1 15:5 |
| %rd 7:5 |
| %sh5 20:5 |
| %sh6 20:6 |
| |
| %sh7 20:7 |
| %csr 20:12 |
| %rm 12:3 |
| %nf 29:3 !function=ex_plus_1 |
| |
| # immediates: |
| %imm_i 20:s12 |
| %imm_s 25:s7 7:5 |
| %imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 |
| %imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 |
| %imm_u 12:s20 !function=ex_shift_12 |
| |
| # Argument sets: |
| &empty |
| &b imm rs2 rs1 |
| &i imm rs1 rd |
| &j imm rd |
| &r rd rs1 rs2 |
| &r2 rd rs1 |
| &r2_s rs1 rs2 |
| &s imm rs1 rs2 |
| &u imm rd |
| &shift shamt rs1 rd |
| &atomic aq rl rs2 rs1 rd |
| &rmrr vm rd rs1 rs2 |
| &rmr vm rd rs2 |
| &r2nfvm vm rd rs1 nf |
| &rnfvm vm rd rs1 rs2 nf |
| |
| # Formats 32: |
| @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd |
| @i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd |
| @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 |
| @s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 |
| @u .................... ..... ....... &u imm=%imm_u %rd |
| @j .................... ..... ....... &j imm=%imm_j %rd |
| |
| @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd |
| @csr ............ ..... ... ..... ....... %csr %rs1 %rd |
| |
| @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd |
| @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd |
| |
| @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd |
| @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd |
| @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd |
| @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd |
| @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd |
| @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd |
| @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd |
| @r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd |
| @r2rd ....... ..... ..... ... ..... ....... %rs2 %rd |
| @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd |
| @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd |
| @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd |
| @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd |
| @r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd |
| @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 |
| |
| @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 |
| @hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 |
| |
| @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 |
| @sfence_vm ....... ..... ..... ... ..... ....... %rs1 |
| |
| # Formats 64: |
| @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd |
| |
| # Formats 128: |
| @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd |
| |
| # *** Privileged Instructions *** |
| ecall 000000000000 00000 000 00000 1110011 |
| ebreak 000000000001 00000 000 00000 1110011 |
| uret 0000000 00010 00000 000 00000 1110011 |
| sret 0001000 00010 00000 000 00000 1110011 |
| mret 0011000 00010 00000 000 00000 1110011 |
| wfi 0001000 00101 00000 000 00000 1110011 |
| sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma |
| sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm |
| |
| # *** RV32I Base Instruction Set *** |
| lui .................... ..... 0110111 @u |
| auipc .................... ..... 0010111 @u |
| jal .................... ..... 1101111 @j |
| jalr ............ ..... 000 ..... 1100111 @i |
| beq ....... ..... ..... 000 ..... 1100011 @b |
| bne ....... ..... ..... 001 ..... 1100011 @b |
| blt ....... ..... ..... 100 ..... 1100011 @b |
| bge ....... ..... ..... 101 ..... 1100011 @b |
| bltu ....... ..... ..... 110 ..... 1100011 @b |
| bgeu ....... ..... ..... 111 ..... 1100011 @b |
| lb ............ ..... 000 ..... 0000011 @i |
| lh ............ ..... 001 ..... 0000011 @i |
| lw ............ ..... 010 ..... 0000011 @i |
| lbu ............ ..... 100 ..... 0000011 @i |
| lhu ............ ..... 101 ..... 0000011 @i |
| sb ....... ..... ..... 000 ..... 0100011 @s |
| sh ....... ..... ..... 001 ..... 0100011 @s |
| sw ....... ..... ..... 010 ..... 0100011 @s |
| addi ............ ..... 000 ..... 0010011 @i |
| slti ............ ..... 010 ..... 0010011 @i |
| sltiu ............ ..... 011 ..... 0010011 @i |
| xori ............ ..... 100 ..... 0010011 @i |
| ori ............ ..... 110 ..... 0010011 @i |
| andi ............ ..... 111 ..... 0010011 @i |
| slli 00000. ...... ..... 001 ..... 0010011 @sh |
| srli 00000. ...... ..... 101 ..... 0010011 @sh |
| srai 01000. ...... ..... 101 ..... 0010011 @sh |
| add 0000000 ..... ..... 000 ..... 0110011 @r |
| sub 0100000 ..... ..... 000 ..... 0110011 @r |
| sll 0000000 ..... ..... 001 ..... 0110011 @r |
| slt 0000000 ..... ..... 010 ..... 0110011 @r |
| sltu 0000000 ..... ..... 011 ..... 0110011 @r |
| xor 0000000 ..... ..... 100 ..... 0110011 @r |
| srl 0000000 ..... ..... 101 ..... 0110011 @r |
| sra 0100000 ..... ..... 101 ..... 0110011 @r |
| or 0000000 ..... ..... 110 ..... 0110011 @r |
| and 0000000 ..... ..... 111 ..... 0110011 @r |
| fence ---- pred:4 succ:4 ----- 000 ----- 0001111 |
| fence_i ---- ---- ---- ----- 001 ----- 0001111 |
| csrrw ............ ..... 001 ..... 1110011 @csr |
| csrrs ............ ..... 010 ..... 1110011 @csr |
| csrrc ............ ..... 011 ..... 1110011 @csr |
| csrrwi ............ ..... 101 ..... 1110011 @csr |
| csrrsi ............ ..... 110 ..... 1110011 @csr |
| csrrci ............ ..... 111 ..... 1110011 @csr |
| |
| # *** RV64I Base Instruction Set (in addition to RV32I) *** |
| lwu ............ ..... 110 ..... 0000011 @i |
| ld ............ ..... 011 ..... 0000011 @i |
| sd ....... ..... ..... 011 ..... 0100011 @s |
| addiw ............ ..... 000 ..... 0011011 @i |
| slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 |
| srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 |
| sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 |
| addw 0000000 ..... ..... 000 ..... 0111011 @r |
| subw 0100000 ..... ..... 000 ..... 0111011 @r |
| sllw 0000000 ..... ..... 001 ..... 0111011 @r |
| srlw 0000000 ..... ..... 101 ..... 0111011 @r |
| sraw 0100000 ..... ..... 101 ..... 0111011 @r |
| |
| # *** RV128I Base Instruction Set (in addition to RV64I) *** |
| ldu ............ ..... 111 ..... 0000011 @i |
| lq ............ ..... 010 ..... 0001111 @i |
| sq ............ ..... 100 ..... 0100011 @s |
| addid ............ ..... 000 ..... 1011011 @i |
| sllid 000000 ...... ..... 001 ..... 1011011 @sh6 |
| srlid 000000 ...... ..... 101 ..... 1011011 @sh6 |
| sraid 010000 ...... ..... 101 ..... 1011011 @sh6 |
| addd 0000000 ..... ..... 000 ..... 1111011 @r |
| subd 0100000 ..... ..... 000 ..... 1111011 @r |
| slld 0000000 ..... ..... 001 ..... 1111011 @r |
| srld 0000000 ..... ..... 101 ..... 1111011 @r |
| srad 0100000 ..... ..... 101 ..... 1111011 @r |
| |
| # *** RV32M Standard Extension *** |
| mul 0000001 ..... ..... 000 ..... 0110011 @r |
| mulh 0000001 ..... ..... 001 ..... 0110011 @r |
| mulhsu 0000001 ..... ..... 010 ..... 0110011 @r |
| mulhu 0000001 ..... ..... 011 ..... 0110011 @r |
| div 0000001 ..... ..... 100 ..... 0110011 @r |
| divu 0000001 ..... ..... 101 ..... 0110011 @r |
| rem 0000001 ..... ..... 110 ..... 0110011 @r |
| remu 0000001 ..... ..... 111 ..... 0110011 @r |
| |
| # *** RV64M Standard Extension (in addition to RV32M) *** |
| mulw 0000001 ..... ..... 000 ..... 0111011 @r |
| divw 0000001 ..... ..... 100 ..... 0111011 @r |
| divuw 0000001 ..... ..... 101 ..... 0111011 @r |
| remw 0000001 ..... ..... 110 ..... 0111011 @r |
| remuw 0000001 ..... ..... 111 ..... 0111011 @r |
| |
| # *** RV128M Standard Extension (in addition to RV64M) *** |
| muld 0000001 ..... ..... 000 ..... 1111011 @r |
| divd 0000001 ..... ..... 100 ..... 1111011 @r |
| divud 0000001 ..... ..... 101 ..... 1111011 @r |
| remd 0000001 ..... ..... 110 ..... 1111011 @r |
| remud 0000001 ..... ..... 111 ..... 1111011 @r |
| |
| # *** RV32A Standard Extension *** |
| lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld |
| sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st |
| amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st |
| amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st |
| amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st |
| amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st |
| amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st |
| amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st |
| amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st |
| amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st |
| amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st |
| |
| # *** RV64A Standard Extension (in addition to RV32A) *** |
| lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld |
| sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st |
| amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st |
| amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st |
| amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st |
| amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st |
| amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st |
| amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st |
| amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st |
| amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st |
| amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st |
| |
| # *** RV32F Standard Extension *** |
| flw ............ ..... 010 ..... 0000111 @i |
| fsw ....... ..... ..... 010 ..... 0100111 @s |
| fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm |
| fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm |
| fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm |
| fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm |
| fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm |
| fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm |
| fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm |
| fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm |
| fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm |
| fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r |
| fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r |
| fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r |
| fmin_s 0010100 ..... ..... 000 ..... 1010011 @r |
| fmax_s 0010100 ..... ..... 001 ..... 1010011 @r |
| fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm |
| fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm |
| fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 |
| feq_s 1010000 ..... ..... 010 ..... 1010011 @r |
| flt_s 1010000 ..... ..... 001 ..... 1010011 @r |
| fle_s 1010000 ..... ..... 000 ..... 1010011 @r |
| fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 |
| fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm |
| fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm |
| fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 |
| |
| # *** RV64F Standard Extension (in addition to RV32F) *** |
| fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm |
| fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm |
| fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm |
| fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm |
| |
| # *** RV32D Standard Extension *** |
| fld ............ ..... 011 ..... 0000111 @i |
| fsd ....... ..... ..... 011 ..... 0100111 @s |
| fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm |
| fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm |
| fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm |
| fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm |
| fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm |
| fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm |
| fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm |
| fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm |
| fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm |
| fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r |
| fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r |
| fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r |
| fmin_d 0010101 ..... ..... 000 ..... 1010011 @r |
| fmax_d 0010101 ..... ..... 001 ..... 1010011 @r |
| fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm |
| fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm |
| feq_d 1010001 ..... ..... 010 ..... 1010011 @r |
| flt_d 1010001 ..... ..... 001 ..... 1010011 @r |
| fle_d 1010001 ..... ..... 000 ..... 1010011 @r |
| fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 |
| fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm |
| fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm |
| fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm |
| fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm |
| |
| # *** RV64D Standard Extension (in addition to RV32D) *** |
| fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm |
| fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm |
| fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 |
| fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm |
| fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm |
| fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 |
| |
| # *** RV32H Base Instruction Set *** |
| hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 |
| hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 |
| hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 |
| hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 |
| hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 |
| hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 |
| hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 |
| hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s |
| hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s |
| hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s |
| hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma |
| hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma |
| |
| # *** RV64H Base Instruction Set *** |
| hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 |
| hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 |
| hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s |
| |
| # *** Vector loads and stores are encoded within LOADFP/STORE-FP *** |
| # Vector unit-stride load/store insns. |
| vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm |
| vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm |
| vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm |
| vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm |
| vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm |
| vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm |
| vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm |
| vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm |
| |
| # Vector unit-stride mask load/store insns. |
| vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2 |
| vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2 |
| |
| # Vector strided insns. |
| vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm |
| vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm |
| vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm |
| vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm |
| vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm |
| vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm |
| vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm |
| vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm |
| |
| # Vector ordered-indexed and unordered-indexed load insns. |
| vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm |
| vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm |
| vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm |
| vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm |
| |
| # Vector ordered-indexed and unordered-indexed store insns. |
| vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm |
| vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm |
| vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm |
| vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm |
| |
| # Vector unit-stride fault-only-first load insns. |
| vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm |
| vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm |
| vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm |
| vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm |
| |
| # Vector whole register insns |
| vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2 |
| vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2 |
| vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2 |
| vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2 |
| vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2 |
| vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2 |
| vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2 |
| vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2 |
| vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2 |
| vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2 |
| vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2 |
| vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2 |
| vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2 |
| vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2 |
| vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2 |
| vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2 |
| vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2 |
| vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2 |
| vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2 |
| vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2 |
| |
| # *** new major opcode OP-V *** |
| vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm |
| vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm |
| vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm |
| vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm |
| vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm |
| vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm |
| vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm |
| vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm |
| vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm |
| vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm |
| vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm |
| vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm |
| vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm |
| vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm |
| vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm |
| vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm |
| vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm |
| vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm |
| vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm |
| vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm |
| vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm |
| vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm |
| vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm |
| vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1 |
| vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1 |
| vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1 |
| vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm |
| vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm |
| vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm |
| vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1 |
| vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1 |
| vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm |
| vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm |
| vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm |
| vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm |
| vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm |
| vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm |
| vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm |
| vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm |
| vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm |
| vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm |
| vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm |
| vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm |
| vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm |
| vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm |
| vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm |
| vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm |
| vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm |
| vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm |
| vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm |
| vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm |
| vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm |
| vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm |
| vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm |
| vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm |
| vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm |
| vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm |
| vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm |
| vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm |
| vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm |
| vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm |
| vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm |
| vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm |
| vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm |
| vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm |
| vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm |
| vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm |
| vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm |
| vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm |
| vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm |
| vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm |
| vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm |
| vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm |
| vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm |
| vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm |
| vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm |
| vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm |
| vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm |
| vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm |
| vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm |
| vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm |
| vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm |
| vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm |
| vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm |
| vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm |
| vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm |
| vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm |
| vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm |
| vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm |
| vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm |
| vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm |
| vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm |
| vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm |
| vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm |
| vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm |
| vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm |
| vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm |
| vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm |
| vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm |
| vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm |
| vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm |
| vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm |
| vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm |
| vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm |
| vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm |
| vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm |
| vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm |
| vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm |
| vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm |
| vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm |
| vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm |
| vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm |
| vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm |
| vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm |
| vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm |
| vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm |
| vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm |
| vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm |
| vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm |
| vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm |
| vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm |
| vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm |
| vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 |
| vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 |
| vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 |
| vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0 |
| vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0 |
| vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0 |
| vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm |
| vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm |
| vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm |
| vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm |
| vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm |
| vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm |
| vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm |
| vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm |
| vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm |
| vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm |
| vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm |
| vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm |
| vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm |
| vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm |
| vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm |
| vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm |
| vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm |
| vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm |
| vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm |
| vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm |
| vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm |
| vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm |
| vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm |
| vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm |
| vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm |
| vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm |
| vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm |
| vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm |
| vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm |
| vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm |
| vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm |
| vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm |
| vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm |
| vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm |
| vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm |
| vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm |
| vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm |
| vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm |
| vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm |
| vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm |
| vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm |
| vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm |
| vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm |
| vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm |
| vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm |
| vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm |
| vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm |
| vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm |
| vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm |
| vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm |
| vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm |
| vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm |
| vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm |
| vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm |
| vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm |
| vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm |
| vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm |
| vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm |
| vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm |
| vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm |
| vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm |
| vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm |
| vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm |
| vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm |
| vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm |
| vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm |
| vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm |
| vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm |
| vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm |
| vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm |
| vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm |
| vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm |
| vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm |
| vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm |
| vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm |
| vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm |
| vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm |
| vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm |
| vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm |
| vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm |
| vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm |
| vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm |
| vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm |
| vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm |
| vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm |
| vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm |
| vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm |
| vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm |
| vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm |
| vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm |
| vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm |
| vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm |
| vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm |
| vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm |
| vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm |
| vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm |
| vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm |
| vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm |
| vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm |
| vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm |
| vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm |
| vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm |
| vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 |
| vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 |
| |
| vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm |
| vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm |
| vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm |
| vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm |
| vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm |
| vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm |
| |
| vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm |
| vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm |
| vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm |
| vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm |
| vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm |
| vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm |
| vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm |
| |
| vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm |
| vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm |
| vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm |
| vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm |
| vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm |
| vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm |
| vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm |
| vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm |
| |
| vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm |
| vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm |
| vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm |
| vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm |
| vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm |
| vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm |
| vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm |
| vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm |
| vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm |
| vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm |
| # Vector ordered and unordered reduction sum |
| vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm |
| vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm |
| vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm |
| # Vector widening ordered and unordered float reduction sum |
| vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm |
| vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r |
| vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r |
| vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r |
| vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r |
| vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r |
| vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r |
| vmorn_mm 011100 - ..... ..... 010 ..... 1010111 @r |
| vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r |
| vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm |
| vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm |
| vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm |
| vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm |
| vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm |
| viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm |
| vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm |
| vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd |
| vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 |
| vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd |
| vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 |
| vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm |
| vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm |
| vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm |
| vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm |
| vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm |
| vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm |
| vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm |
| vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm |
| vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm |
| vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm |
| vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r |
| vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd |
| vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd |
| vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd |
| vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd |
| |
| # Vector Integer Extension |
| vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm |
| vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm |
| vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm |
| vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm |
| vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm |
| vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm |
| |
| vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 |
| vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 |
| vsetvl 1000000 ..... ..... 111 ..... 1010111 @r |
| |
| # *** RV32 Zba Standard Extension *** |
| sh1add 0010000 .......... 010 ..... 0110011 @r |
| sh2add 0010000 .......... 100 ..... 0110011 @r |
| sh3add 0010000 .......... 110 ..... 0110011 @r |
| |
| # *** RV64 Zba Standard Extension (in addition to RV32 Zba) *** |
| add_uw 0000100 .......... 000 ..... 0111011 @r |
| sh1add_uw 0010000 .......... 010 ..... 0111011 @r |
| sh2add_uw 0010000 .......... 100 ..... 0111011 @r |
| sh3add_uw 0010000 .......... 110 ..... 0111011 @r |
| slli_uw 00001 ............ 001 ..... 0011011 @sh |
| |
| # *** RV32 Zbb Standard Extension *** |
| andn 0100000 .......... 111 ..... 0110011 @r |
| clz 011000 000000 ..... 001 ..... 0010011 @r2 |
| cpop 011000 000010 ..... 001 ..... 0010011 @r2 |
| ctz 011000 000001 ..... 001 ..... 0010011 @r2 |
| max 0000101 .......... 110 ..... 0110011 @r |
| maxu 0000101 .......... 111 ..... 0110011 @r |
| min 0000101 .......... 100 ..... 0110011 @r |
| minu 0000101 .......... 101 ..... 0110011 @r |
| orc_b 001010 000111 ..... 101 ..... 0010011 @r2 |
| orn 0100000 .......... 110 ..... 0110011 @r |
| # The encoding for rev8 differs between RV32 and RV64. |
| # rev8_32 denotes the RV32 variant. |
| rev8_32 011010 011000 ..... 101 ..... 0010011 @r2 |
| rol 0110000 .......... 001 ..... 0110011 @r |
| ror 0110000 .......... 101 ..... 0110011 @r |
| rori 01100 ............ 101 ..... 0010011 @sh |
| sext_b 011000 000100 ..... 001 ..... 0010011 @r2 |
| sext_h 011000 000101 ..... 001 ..... 0010011 @r2 |
| xnor 0100000 .......... 100 ..... 0110011 @r |
| # The encoding for zext.h differs between RV32 and RV64. |
| # zext_h_32 denotes the RV32 variant. |
| zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2 |
| |
| # *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** |
| clzw 0110000 00000 ..... 001 ..... 0011011 @r2 |
| ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 |
| cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 |
| # The encoding for rev8 differs between RV32 and RV64. |
| # When executing on RV64, the encoding used in RV32 is an illegal |
| # instruction, so we use different handler functions to differentiate. |
| rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 |
| rolw 0110000 .......... 001 ..... 0111011 @r |
| roriw 0110000 .......... 101 ..... 0011011 @sh5 |
| rorw 0110000 .......... 101 ..... 0111011 @r |
| # The encoding for zext.h differs between RV32 and RV64. |
| # When executing on RV64, the encoding used in RV32 is an illegal |
| # instruction, so we use different handler functions to differentiate. |
| zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 |
| |
| # *** RV32 Zbc Standard Extension *** |
| clmul 0000101 .......... 001 ..... 0110011 @r |
| clmulh 0000101 .......... 011 ..... 0110011 @r |
| clmulr 0000101 .......... 010 ..... 0110011 @r |
| |
| # *** RV32 Zbs Standard Extension *** |
| bclr 0100100 .......... 001 ..... 0110011 @r |
| bclri 01001. ........... 001 ..... 0010011 @sh |
| bext 0100100 .......... 101 ..... 0110011 @r |
| bexti 01001. ........... 101 ..... 0010011 @sh |
| binv 0110100 .......... 001 ..... 0110011 @r |
| binvi 01101. ........... 001 ..... 0010011 @sh |
| bset 0010100 .......... 001 ..... 0110011 @r |
| bseti 00101. ........... 001 ..... 0010011 @sh |
| |
| # *** RV32 Zfh Extension *** |
| flh ............ ..... 001 ..... 0000111 @i |
| fsh ....... ..... ..... 001 ..... 0100111 @s |
| fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm |
| fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm |
| fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm |
| fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm |
| fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm |
| fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm |
| fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm |
| fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm |
| fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm |
| fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r |
| fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r |
| fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r |
| fmin_h 0010110 ..... ..... 000 ..... 1010011 @r |
| fmax_h 0010110 ..... ..... 001 ..... 1010011 @r |
| fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm |
| fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm |
| fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm |
| fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm |
| fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm |
| fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm |
| fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2 |
| feq_h 1010010 ..... ..... 010 ..... 1010011 @r |
| flt_h 1010010 ..... ..... 001 ..... 1010011 @r |
| fle_h 1010010 ..... ..... 000 ..... 1010011 @r |
| fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2 |
| fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm |
| fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm |
| fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2 |
| |
| # *** RV64 Zfh Extension (in addition to RV32 Zfh) *** |
| fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm |
| fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm |
| fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm |
| fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm |
| |
| # *** Svinval Standard Extension *** |
| sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma |
| sfence_w_inval 0001100 00000 00000 000 00000 1110011 |
| sfence_inval_ir 0001100 00001 00000 000 00000 1110011 |
| hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma |
| hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma |
