commit 2c8f2e895374716eb5a1191b16fac6ebaf17ec74
author Brian Swetland <swetland@google.com> Sun Jan 07 15:12:03 2018 -0800
committer Petr Hosek <phosek@google.com> Fri Dec 13 03:32:05 2019 -0800
tree aba4a42dfd530daed0d2fb19ed61335044440066
parent a4c669ca3510d41def15ff87445541e085643d4d

nvme: support msi as well as msix

Change-Id: I63880e25ac245f61cb807810453cb7b852be3e87

hw/block/nvme.c

diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 12d8254..bb05701 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -28,6 +28,7 @@
 #include "qemu/osdep.h"
 #include "qemu/units.h"
 #include "hw/block/block.h"
+#include "hw/pci/msi.h"
 #include "hw/pci/msix.h"
 #include "hw/pci/pci.h"
 #include "hw/qdev-properties.h"
@@ -111,7 +112,9 @@
 static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
 {
     if (cq->irq_enabled) {
-        if (msix_enabled(&(n->parent_obj))) {
+        if (msi_enabled(&(n->parent_obj))) {
+            msi_notify(&(n->parent_obj), cq->vector);
+        } else if (msix_enabled(&(n->parent_obj))) {
             trace_nvme_irq_msix(cq->vector);
             msix_notify(&(n->parent_obj), cq->vector);
         } else {
@@ -1358,6 +1361,7 @@
         PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,
         &n->iomem);
     msix_init_exclusive_bar(pci_dev, n->num_queues, 4, NULL);
+    msi_init(pci_dev, 0, n->num_queues, true, false, NULL);
 
     id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
     id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
@@ -1446,13 +1450,14 @@
         g_free(n->cmbuf);
     }
     msix_uninit_exclusive_bar(pci_dev);
+    msi_uninit(&n->parent_obj);
 }
 
 static Property nvme_props[] = {
     DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
     DEFINE_PROP_STRING("serial", NvmeCtrl, serial),
     DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, cmb_size_mb, 0),
-    DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 64),
+    DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 32),
     DEFINE_PROP_END_OF_LIST(),
 };