blob: dbe6da9a737cdf6136efed714587cd86d5670a87 [file] [log] [blame]
; Copyright (c) 2020-2021, Intel Corporation
;
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; modification, are permitted provided that the following conditions are met:
;
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; this list of conditions and the following disclaimer in the documentation
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; SKZ84: Use of VMX TSC Scaling or TSC Offsetting Will Result in
; Corrupted Intel PT Packets
;
; When Intel(R) PT (Processor Trace) is enabled within a VMX (Virtual
; Machine Extensions) guest, and TSC (Time Stamp Counter) offsetting or
; TSC scaling is enabled for that guest, by setting primary
; processor-based execution control bit 3 or secondary processor-based
; execution control bit 25, respectively, in the VMCS (Virtual Machine
; Control Structure) for that guest, any TMA (TSC(MTC Alignment) packet
; generated will have corrupted values in the CTC (Core Timer Copy) and
; FastCounter fields. Additionally, the corrupted TMA packet will be
; followed by a bogus data byte.
;
; cpu 6/85
; cpu 6/106
; cpu 6/108
; cpu 6/143
;
org 0x100000
bits 64
; @pt p0: psb()
; @pt p1: fup(3: %l0)
; @pt p2: mode.exec(64bit)
; @pt p3: psbend()
l0: nop
; @pt p4: raw-8(0x02)
; @pt raw-8(0x73)
; @pt raw-8(0x01)
; @pt raw-8(0x01)
; @pt raw-8(0x01)
; @pt raw-8(0x01)
; @pt raw-8(0x00)
; @pt raw-8(0x00)
l1: hlt
; @pt p5: fup(1: %l1)
; @pt p6: tip.pgd(0: %l1)
; @pt .exp(ptdump)
;%0p0 psb
;%0p1 fup 3: %?l0
;%0p2 mode.exec cs.l
;%0p3 psbend
;%0p4 <invalid>
;%0p5 fup 1: %?l1.2
;%0p6 tip.pgd 0: %?l1.0
; @pt .exp(ptxed)
;%0l0 # nop
;[disabled]