| ; Copyright (c) 2017-2021, Intel Corporation |
| ; |
| ; Redistribution and use in source and binary forms, with or without |
| ; modification, are permitted provided that the following conditions are met: |
| ; |
| ; * Redistributions of source code must retain the above copyright notice, |
| ; this list of conditions and the following disclaimer. |
| ; * Redistributions in binary form must reproduce the above copyright notice, |
| ; this list of conditions and the following disclaimer in the documentation |
| ; and/or other materials provided with the distribution. |
| ; * Neither the name of Intel Corporation nor the names of its contributors |
| ; may be used to endorse or promote products derived from this software |
| ; without specific prior written permission. |
| ; |
| ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| ; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| ; POSSIBILITY OF SUCH DAMAGE. |
| |
| ; Test SWITCH_CPU_WIDE in perf_event sideband. |
| ; |
| ; Variant: ring-3 tracing |
| ; timing is off - delay the event application |
| ; |
| ; opt:ptdump --sb:compact --sb:offset |
| ; opt:ptxed --event:tick --sb:compact --sb:offset --sb:switch |
| ; |
| |
| org 0x1000 |
| bits 64 |
| |
| |
| ; @sb primary(pevent) |
| ; @sb pevent-sample_type(time) |
| ; @sb s0: pevent-mmap-section(text_1, 1, 1, 0x0) |
| ; @sb s1: pevent-mmap-section(text_2, 2, 2, 0x0) |
| ; @sb s2: pevent-itrace-start(1, 1, 0x0) |
| |
| section text_1 vstart=0x1000 start=0x1000 |
| ; @pt p0: psb() |
| ; @pt p1: mode.exec(64bit) |
| ; @pt p2: tsc(0x1) |
| ; @pt p3: fup(3: %l0) |
| ; @pt p4: psbend() |
| l0: call rax |
| l1: hlt |
| |
| ; @sb s3: pevent-switch-cpu-wide.out(2, 2, 0x2) |
| ; @sb s4: pevent-switch-cpu-wide.in(1, 1, 0x3) |
| |
| ; @pt p5: tsc(0x3) |
| ; @pt p6: tip(1: %l2) |
| l2: nop |
| |
| ; @pt p7: fup(1: %l3) |
| ; @pt p8: tip.pgd(0: %l3) |
| l3: hlt |
| |
| section text_2 vstart=0x2000 start=0x1010 |
| ; @pt p9: tip.pge(3: %l4) |
| l4: nop |
| |
| ; @pt p10: fup(1: %l5) |
| ; @pt p11: tip.pgd(0: %l5) |
| l5: hlt |
| |
| |
| ; @pt .exp(ptdump) |
| ;%0p0 psb |
| ;%0p1 mode.exec cs.l |
| ;%0s0 PERF_RECORD_MMAP 1/1, 1000, 5, 0, pevent-tip_pgd-switch_cpu_wide-tsc-tip_pge.bin { 0 } |
| ;%0s1 PERF_RECORD_MMAP 2/2, 2000, 2, 10, pevent-tip_pgd-switch_cpu_wide-tsc-tip_pge.bin { 0 } |
| ;%0s2 PERF_RECORD_ITRACE_START 1/1 { 0 } |
| ;%0p2 tsc 1 |
| ;%0p3 fup 3: %?l0 |
| ;%0p4 psbend |
| ;%0s3 PERF_RECORD_SWITCH_CPU_WIDE.OUT 2/2 { 2 } |
| ;%0s4 PERF_RECORD_SWITCH_CPU_WIDE.IN 1/1 { 3 } |
| ;%0p5 tsc 3 |
| ;%0p6 tip 1: %?l2.2 |
| ;%0p7 fup 1: %?l3.2 |
| ;%0p8 tip.pgd 0: %?l3.0 |
| ;%0p9 tip.pge 3: %?l4 |
| ;%0p10 fup 1: %?l5.2 |
| ;%0p11 tip.pgd 0: %?l5.0 |
| |
| |
| ; @pt .exp(ptxed) |
| ;%0s0 PERF_RECORD_MMAP 1/1, 1000, 5, 0, pevent-tip_pgd-switch_cpu_wide-tsc-tip_pge.bin { 0 } |
| ;%0s1 PERF_RECORD_MMAP 2/2, 2000, 2, 10, pevent-tip_pgd-switch_cpu_wide-tsc-tip_pge.bin { 0 } |
| ;%0s2 PERF_RECORD_ITRACE_START 1/1 { 0 } |
| ;[context: pid-1] |
| ;%0l0 # call rax |
| ;[tick] |
| ;%0s3 PERF_RECORD_SWITCH_CPU_WIDE.OUT 2/2 { 2 } |
| ;%0s4 PERF_RECORD_SWITCH_CPU_WIDE.IN 1/1 { 3 } |
| ;%0l2 # nop |
| ;[disabled] |
| ;[context: pid-2] |
| ;[enabled] |
| ;%0l4 # nop |
| ;[disabled] |