| ; Copyright (c) 2018-2019, Intel Corporation |
| ; |
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| |
| ; SKL168: Intel(R) PT CYC Packets Can be Dropped When Immediately Preceding PSB |
| ; |
| ; Due to a rare microarchitectural condition, generation of an Intel PT |
| ; (Processor Trace) PSB (Packet Stream Boundary) packet can cause a |
| ; single CYC (Cycle Count) packet, possibly along with an associated |
| ; MTC (Mini Time Counter) packet, to be dropped. |
| ; |
| ; Variant: MTC and corresponding CYC packet dropped |
| ; |
| ; opt:ptdump --tcal --time-delta |
| ; opt:ptdump --mtc-freq 4 --cpuid-0x15.eax 1 --cpuid-0x15.ebx 4 |
| ; |
| ; cpu 6/78 |
| ; cpu 6/94 |
| ; cpu 6/142 |
| ; cpu 6/158 |
| ; |
| |
| org 0x100000 |
| bits 64 |
| |
| ; @pt p1: psb() |
| ; @pt p2: psbend() |
| |
| ; @pt p3: mtc(0x1) |
| ; @pt p4: cyc(0x100) |
| ; @pt p5: mtc(0x2) |
| ; @pt p6: cyc(0x80) |
| ; @pt p7: psb() |
| ; @pt p8: psbend() |
| ; @pt p9: cyc(0x100) |
| ; @pt p10: mtc(0x4) |
| ; @pt p11: cyc(0x100) |
| ; @pt p12: mtc(0x5) |
| |
| |
| ; @pt .exp(ptdump) |
| ;%0p1 psb |
| ;%0p2 psbend |
| ;[%p3: error printing time: no timing information] |
| ;%0p3 mtc 1 fcr <unavailable> |
| ;[%p4: calibration error: no timing information] |
| ;[%p4: error updating time: no calibration] |
| ;%0p4 cyc 100 |
| ;%0p5 mtc 2 fcr +0.250 |
| ;%0p6 cyc 80 |
| ;%0p7 psb |
| ;%0p8 psbend |
| ;%0p9 cyc 100 |
| ;%0p10 mtc 4 fcr +0.000 |
| ;%0p11 cyc 100 |
| ;%0p12 mtc 5 fcr +0.000 |