| <?xml version="1.0" encoding="UTF-8"?> |
| <!-- |
| Copyright © 2020 Google, Inc. |
| |
| Permission is hereby granted, free of charge, to any person obtaining a |
| copy of this software and associated documentation files (the "Software"), |
| to deal in the Software without restriction, including without limitation |
| the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| and/or sell copies of the Software, and to permit persons to whom the |
| Software is furnished to do so, subject to the following conditions: |
| |
| The above copyright notice and this permission notice (including the next |
| paragraph) shall be included in all copies or substantial portions of the |
| Software. |
| |
| THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| SOFTWARE. |
| --> |
| |
| <isa> |
| |
| <!-- |
| Helpers for cat2/cat3 nop encoding, which re-uses the SRC1_R/SRC2_R |
| fields to encode a # of nop delay slots following the instruction. |
| --> |
| |
| <expr name="#cat2-cat3-nop-encoding"> |
| (({SRC1_R} != 0) || ({SRC2_R} != 0)) && ({REPEAT} == 0) |
| </expr> |
| |
| <expr name="#cat2-cat3-nop-value"> |
| {SRC1_R} | ({SRC2_R} << 1) |
| </expr> |
| |
| <!-- |
| Source/Dest gpr encoding. In the gpr case, this handles the special |
| cases (p0.x/a0.x) |
| --> |
| |
| <expr name="#reg-gpr-a0"> |
| {GPR} == 61 /* a0.* */ |
| </expr> |
| |
| <expr name="#reg-gpr-p0"> |
| {GPR} == 62 /* p0.x */ |
| </expr> |
| |
| <bitset name="#reg-gpr" size="8"> |
| <override expr="#reg-gpr-a0"> |
| <display> |
| a0.{SWIZ} |
| </display> |
| <assert low="2" high="7">111101</assert> |
| </override> |
| <override expr="#reg-gpr-p0"> |
| <display> |
| p0.{SWIZ} |
| </display> |
| <assert low="2" high="7">111110</assert> |
| </override> |
| <display> |
| r{GPR}.{SWIZ} |
| </display> |
| <field name="SWIZ" low="0" high="1" type="#swiz"/> |
| <field name="GPR" low="2" high="7" type="uint"/> |
| <encode type="struct ir3_register *"> |
| <map name="GPR">src->num >> 2</map> |
| <map name="SWIZ">src->num & 0x3</map> |
| </encode> |
| </bitset> |
| |
| <bitset name="#reg-const" size="11"> |
| <display> |
| c{CONST}.{SWIZ} |
| </display> |
| <field name="SWIZ" low="0" high="1" type="#swiz"/> |
| <field name="CONST" low="2" high="10" type="uint"/> |
| <encode type="struct ir3_register *"> |
| <map name="CONST">src->num >> 2</map> |
| <map name="SWIZ">src->num & 0x3</map> |
| </encode> |
| </bitset> |
| |
| <expr name="#offset-zero"> |
| {OFFSET} == 0 |
| </expr> |
| |
| <bitset name="#reg-relative-gpr" size="10"> |
| <override expr="#offset-zero"> |
| <display> |
| r<a0.x> |
| </display> |
| </override> |
| <display> |
| r<a0.x + {OFFSET}> |
| </display> |
| <field name="OFFSET" low="0" high="9" type="int"/> |
| <encode type="struct ir3_register *"> |
| <map name="OFFSET">src->array.offset</map> |
| </encode> |
| </bitset> |
| |
| <bitset name="#reg-relative-const" size="10"> |
| <override expr="#offset-zero"> |
| <display> |
| c<a0.x> |
| </display> |
| </override> |
| <display> |
| c<a0.x + {OFFSET}> |
| </display> |
| <field name="OFFSET" low="0" high="9" type="int"/> |
| <encode type="struct ir3_register *"> |
| <map name="OFFSET">src->array.offset</map> |
| </encode> |
| </bitset> |
| |
| <!-- |
| Source Register encoding, used in cat2 and cat4 where a src can be |
| either gpr/const/relative |
| --> |
| |
| <bitset name="#multisrc" size="16"> |
| <doc> |
| Encoding for instruction source which can be GPR/CONST/IMMED |
| or relative GPR/CONST. |
| </doc> |
| <encode type="struct ir3_register *" case-prefix="REG_"> |
| <map name="ABSNEG">extract_ABSNEG(src)</map> |
| <map name="SRC">src</map> |
| </encode> |
| </bitset> |
| |
| <bitset name="#mulitsrc-immed" extends="#multisrc"> |
| <override expr="#multisrc-half"> |
| <display> |
| {ABSNEG}{SRC_R}h({IMMED}) |
| </display> |
| </override> |
| <display> |
| {ABSNEG}{SRC_R}{IMMED} |
| </display> |
| <field name="IMMED" low="0" high="10" type="int"/> |
| <pattern low="11" high="13">100</pattern> |
| <field name="ABSNEG" low="14" high="15" type="#absneg"/> |
| <encode> |
| <map name="IMMED">extract_reg_iim(src)</map> |
| </encode> |
| </bitset> |
| |
| <bitset name="#mulitsrc-immed-flut" extends="#multisrc"> |
| <doc> |
| Immediate with int->float lookup table: |
| |
| 0 -> 0.0 |
| 1 -> 0.5 |
| 2 -> 1.0 |
| 3 -> 2.0 |
| 4 -> e |
| 5 -> pi |
| 6 -> 1/pi |
| 7 -> 1/log2(e) |
| 8 -> log2(e) |
| 9 -> 1/log2(10) |
| 10 -> log2(10) |
| 11 -> 4.0 |
| |
| </doc> |
| <field name="IMMED" low="0" high="9" type="#flut"/> |
| <pattern low="11" high="13">101</pattern> |
| <field name="ABSNEG" low="14" high="15" type="#absneg"/> |
| <encode> |
| <map name="IMMED">extract_reg_uim(src)</map> |
| </encode> |
| </bitset> |
| |
| <bitset name="#multisrc-immed-flut-full" extends="#mulitsrc-immed-flut"> |
| <display> |
| {ABSNEG}{SRC_R}{IMMED} |
| </display> |
| <pattern pos="10">0</pattern> |
| </bitset> |
| |
| <bitset name="#multisrc-immed-flut-half" extends="#mulitsrc-immed-flut"> |
| <display> |
| {ABSNEG}{SRC_R}h{IMMED} |
| </display> |
| <pattern pos="10">1</pattern> |
| </bitset> |
| |
| <expr name="#multisrc-half"> |
| !{FULL} |
| </expr> |
| |
| <bitset name="#multisrc-gpr" extends="#multisrc"> |
| <display> |
| {ABSNEG}{SRC_R}{HALF}{SRC} |
| </display> |
| <derived name="HALF" expr="#multisrc-half" type="bool" display="h"/> |
| <field name="SRC" low="0" high="7" type="#reg-gpr"/> |
| <pattern low="8" high="13">000000</pattern> |
| <field name="ABSNEG" low="14" high="15" type="#absneg"/> |
| </bitset> |
| |
| <bitset name="#multisrc-const" extends="#multisrc"> |
| <display> |
| {ABSNEG}{SRC_R}{HALF}{SRC} |
| </display> |
| <derived name="HALF" expr="#multisrc-half" type="bool" display="h"/> |
| <field name="SRC" low="0" high="10" type="#reg-const"/> |
| <pattern low="11" high="13">x10</pattern> |
| <field name="ABSNEG" low="14" high="15" type="#absneg"/> |
| </bitset> |
| |
| <bitset name="#multisrc-relative" extends="#multisrc"> |
| <pattern low="11" high="13">001</pattern> |
| <field name="ABSNEG" low="14" high="15" type="#absneg"/> |
| </bitset> |
| |
| <bitset name="#multisrc-relative-gpr" extends="#multisrc-relative"> |
| <display> |
| {ABSNEG}{SRC_R}{HALF}{SRC} |
| </display> |
| <derived name="HALF" expr="#multisrc-half" type="bool" display="h"/> |
| <field name="SRC" low="0" high="9" type="#reg-relative-gpr"/> |
| <pattern pos="10">0</pattern> |
| </bitset> |
| |
| <bitset name="#multisrc-relative-const" extends="#multisrc-relative"> |
| <display> |
| {ABSNEG}{SRC_R}{HALF}{SRC} |
| </display> |
| <derived name="HALF" expr="#multisrc-half" type="bool" display="h"/> |
| <field name="SRC" low="0" high="9" type="#reg-relative-const"/> |
| <pattern pos="10">1</pattern> |
| </bitset> |
| |
| <!-- |
| For cat2/cat4, the dst reg is full precision if {FULL} == {DEST_CONV} |
| In addition, for cat2 instructions that can write p0.x (cmps.*, and.b, |
| xor.b, etc), p0.x is never half (DEST_CONV is ignored) |
| --> |
| <expr name="#dest-half"> |
| ({FULL} == {DST_CONV}) && ({DST} <= 0xf7 /* p0.x */) |
| </expr> |
| |
| <expr name="#true"> |
| 1 |
| </expr> |
| |
| <expr name="#false"> |
| 0 |
| </expr> |
| |
| <!-- These make #true/#false a bit redundant, but I guess keep them for clarity --> |
| <expr name="#zero"> |
| 0 |
| </expr> |
| <expr name="#one"> |
| 1 |
| </expr> |
| <expr name="#two"> |
| 2 |
| </expr> |
| |
| <!-- |
| Enums used in various places: |
| --> |
| |
| <enum name="#rptN"> |
| <value val="0" display=""/> |
| <value val="1" display="(rpt1)"/> |
| <value val="2" display="(rpt2)"/> |
| <value val="3" display="(rpt3)"/> |
| <value val="4" display="(rpt4)"/> |
| <value val="5" display="(rpt5)"/> |
| </enum> |
| |
| <enum name="#cond"> |
| <value val="0" display="lt"/> |
| <value val="1" display="le"/> |
| <value val="2" display="gt"/> |
| <value val="3" display="ge"/> |
| <value val="4" display="eq"/> |
| <value val="5" display="ne"/> |
| </enum> |
| |
| <enum name="#swiz"> |
| <value val="0" display="x"/> |
| <value val="1" display="y"/> |
| <value val="2" display="z"/> |
| <value val="3" display="w"/> |
| </enum> |
| |
| <enum name="#type"> |
| <value val="0" display="f16"/> |
| <value val="1" display="f32"/> |
| <value val="2" display="u16"/> |
| <value val="3" display="u32"/> |
| <value val="4" display="s16"/> |
| <value val="5" display="s32"/> |
| <value val="6" display="u8"/> |
| <value val="7" display="s8"/> |
| </enum> |
| |
| <expr name="#type-half"> |
| ({TYPE} == 0) /* f16 */ || |
| ({TYPE} == 2) /* u16 */ || |
| ({TYPE} == 4) /* s16 */ || |
| ({TYPE} == 6) /* u8 */ || |
| ({TYPE} == 7) /* s8 */ |
| </expr> |
| |
| <enum name="#absneg"> |
| <value val="0" display=""/> |
| <value val="1" display="(neg)"/> |
| <value val="2" display="(abs)"/> |
| <value val="3" display="(absneg)"/> |
| </enum> |
| |
| <enum name="#flut"> |
| <doc>int to float lookup table</doc> |
| <value val="0" display="(0.0)"/> |
| <value val="1" display="(0.5)"/> |
| <value val="2" display="(1.0)"/> |
| <value val="3" display="(2.0)"/> |
| <value val="4" display="(e)"/> |
| <value val="5" display="(pi)"/> |
| <value val="6" display="(1/pi)"/> |
| <value val="7" display="(1/log2(e))"/> |
| <value val="8" display="(log2(e))"/> |
| <value val="9" display="(1/log2(10))"/> |
| <value val="10" display="(log2(10))"/> |
| <value val="11" display="(4.0)"/> |
| </enum> |
| |
| <enum name="#wrmask"> |
| <value val="0" display=""/> |
| <value val="1" display="x"/> |
| <value val="2" display="y"/> |
| <value val="3" display="xy"/> |
| <value val="4" display="z"/> |
| <value val="5" display="zx"/> |
| <value val="6" display="zy"/> |
| <value val="7" display="xyz"/> |
| <value val="8" display="w"/> |
| <value val="9" display="xw"/> |
| <value val="10" display="yw"/> |
| <value val="11" display="xyw"/> |
| <value val="12" display="zw"/> |
| <value val="13" display="xzw"/> |
| <value val="14" display="yzw"/> |
| <value val="15" display="xyzw"/> |
| </enum> |
| |
| </isa> |