commit fa8708ab4887efbf6baa366d492746f37206cd67
author Josh Gargus <jjosh@google.com> Thu Apr 25 03:00:30 2024 +0000
committer CQ Bot <fuchsia-internal-scoped@luci-project-accounts.iam.gserviceaccount.com> Thu May 02 16:29:39 2024 +0000
tree 0c3b7ba593a0c89c7ca4b7e7a8c8ec6b0a40dd84
parent 42378d506c3d5cc2d92e0a47181100f1ca301875

[fuchsia/lavapipe] ARM fix.

Change-Id: Ib0fa2df5d3fe30ddda554eac27fb3726541fd713
Reviewed-on: https://fuchsia-review.googlesource.com/c/third_party/mesa/+/1036241
Fuchsia-Auto-Submit: Josh Gargus <jjosh@google.com>
Reviewed-by: John Bauman <jbauman@google.com>
Commit-Queue: Auto-Submit <auto-submit@fuchsia-infra.iam.gserviceaccount.com>

src/gallium/auxiliary/gallivm/lp_bld_fuchsia_memory_mapper.cpp

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_fuchsia_memory_mapper.cpp b/src/gallium/auxiliary/gallivm/lp_bld_fuchsia_memory_mapper.cpp
index da43148..37a7060 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_fuchsia_memory_mapper.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_fuchsia_memory_mapper.cpp
@@ -226,10 +226,11 @@
 
 #if defined(__arm__) || defined(__aarch64__)
     // Certain ARM implementations treat icache clear instruction as a memory read,
-    // and CPU segfaults on trying to clear cache on !PROT_READ page.  Therefore we need
-    // to temporarily add PROT_READ for the sake of flushing the instruction caches.
-    if (InvalidateCache && !(Protect & PROT_READ)) {
-        Memory::InvalidateInstructionCache(Block.base(), Block.allocatedSize());
+    // and CPU segfaults on trying to clear cache on !ZX_VM_FLAG_PERM_READ page.
+    // Therefore we need to temporarily add ZX_VM_FLAG_PERM_READ for the sake of
+    // flushing the instruction caches.
+    if (InvalidateCache && !(Protect & ZX_VM_FLAG_PERM_READ)) {
+        llvm::sys::Memory::Memory::InvalidateInstructionCache(Block.base(), Block.allocatedSize());
         InvalidateCache = false;
     }
 #endif