src/freedreno/registers/a6xx.xml

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>
<import file="adreno/adreno_pm4.xml"/>

<!-- these might be same as a5xx -->
<enum name="a6xx_color_fmt">
	<value value="0x02" name="RB6_A8_UNORM"/>
	<value value="0x03" name="RB6_R8_UNORM"/>
	<value value="0x04" name="RB6_R8_SNORM"/>
	<value value="0x05" name="RB6_R8_UINT"/>
	<value value="0x06" name="RB6_R8_SINT"/>
	<value value="0x08" name="RB6_R4G4B4A4_UNORM"/>
	<value value="0x0a" name="RB6_R5G5B5A1_UNORM"/>
	<value value="0x0e" name="RB6_R5G6B5_UNORM"/>
	<value value="0x0f" name="RB6_R8G8_UNORM"/>
	<value value="0x10" name="RB6_R8G8_SNORM"/>
	<value value="0x11" name="RB6_R8G8_UINT"/>
	<value value="0x12" name="RB6_R8G8_SINT"/>
	<value value="0x15" name="RB6_R16_UNORM"/>
	<value value="0x16" name="RB6_R16_SNORM"/>
	<value value="0x17" name="RB6_R16_FLOAT"/>
	<value value="0x18" name="RB6_R16_UINT"/>
	<value value="0x19" name="RB6_R16_SINT"/>
	<value value="0x30" name="RB6_R8G8B8A8_UNORM"/>
	<value value="0x31" name="RB6_R8G8B8_UNORM"/>
	<value value="0x32" name="RB6_R8G8B8A8_SNORM"/>
	<value value="0x33" name="RB6_R8G8B8A8_UINT"/>
	<value value="0x34" name="RB6_R8G8B8A8_SINT"/>
	<value value="0x37" name="RB6_R10G10B10A2_UNORM"/>  <!-- GL_RGB10_A2 -->
	<value value="0x3a" name="RB6_R10G10B10A2_UINT"/>   <!-- GL_RGB10_A2UI -->
	<value value="0x42" name="RB6_R11G11B10_FLOAT"/>    <!-- GL_R11F_G11F_B10F -->
	<value value="0x43" name="RB6_R16G16_UNORM"/>
	<value value="0x44" name="RB6_R16G16_SNORM"/>
	<value value="0x45" name="RB6_R16G16_FLOAT"/>
	<value value="0x46" name="RB6_R16G16_UINT"/>
	<value value="0x47" name="RB6_R16G16_SINT"/>
	<value value="0x4a" name="RB6_R32_FLOAT"/>
	<value value="0x4b" name="RB6_R32_UINT"/>
	<value value="0x4c" name="RB6_R32_SINT"/>
	<value value="0x60" name="RB6_R16G16B16A16_UNORM"/>
	<value value="0x61" name="RB6_R16G16B16A16_SNORM"/>
	<value value="0x62" name="RB6_R16G16B16A16_FLOAT"/>
	<value value="0x63" name="RB6_R16G16B16A16_UINT"/>
	<value value="0x64" name="RB6_R16G16B16A16_SINT"/>
	<value value="0x67" name="RB6_R32G32_FLOAT"/>
	<value value="0x68" name="RB6_R32G32_UINT"/>
	<value value="0x69" name="RB6_R32G32_SINT"/>
	<value value="0x82" name="RB6_R32G32B32A32_FLOAT"/>
	<value value="0x83" name="RB6_R32G32B32A32_UINT"/>
	<value value="0x84" name="RB6_R32G32B32A32_SINT"/>
	<value value="0x91" name="RB6_Z24_UNORM_S8_UINT"/>
	<value value="0xa0" name="RB6_X8Z24_UNORM"/>
</enum>

<!-- these might be same as a5xx -->
<enum name="a6xx_tile_mode">
	<value name="TILE6_LINEAR" value="0"/>
	<value name="TILE6_2" value="2"/>
	<value name="TILE6_3" value="3"/>
</enum>

<!-- these might be same as a5xx -->
<enum name="a6xx_vtx_fmt" prefix="chipset">
	<value value="0x03" name="VFMT6_8_UNORM"/>
	<value value="0x04" name="VFMT6_8_SNORM"/>
	<value value="0x05" name="VFMT6_8_UINT"/>
	<value value="0x06" name="VFMT6_8_SINT"/>

	<value value="0x0f" name="VFMT6_8_8_UNORM"/>
	<value value="0x10" name="VFMT6_8_8_SNORM"/>
	<value value="0x11" name="VFMT6_8_8_UINT"/>
	<value value="0x12" name="VFMT6_8_8_SINT"/>

	<value value="0x15" name="VFMT6_16_UNORM"/>
	<value value="0x16" name="VFMT6_16_SNORM"/>
	<value value="0x17" name="VFMT6_16_FLOAT"/>
	<value value="0x18" name="VFMT6_16_UINT"/>
	<value value="0x19" name="VFMT6_16_SINT"/>

	<value value="0x21" name="VFMT6_8_8_8_UNORM"/>
	<value value="0x22" name="VFMT6_8_8_8_SNORM"/>
	<value value="0x23" name="VFMT6_8_8_8_UINT"/>
	<value value="0x24" name="VFMT6_8_8_8_SINT"/>

	<value value="0x30" name="VFMT6_8_8_8_8_UNORM"/>
	<value value="0x32" name="VFMT6_8_8_8_8_SNORM"/>
	<value value="0x33" name="VFMT6_8_8_8_8_UINT"/>
	<value value="0x34" name="VFMT6_8_8_8_8_SINT"/>

	<value value="0x36" name="VFMT6_10_10_10_2_UNORM"/>
	<value value="0x39" name="VFMT6_10_10_10_2_SNORM"/>
	<value value="0x3a" name="VFMT6_10_10_10_2_UINT"/>
	<value value="0x3b" name="VFMT6_10_10_10_2_SINT"/>

	<value value="0x42" name="VFMT6_11_11_10_FLOAT"/>

	<value value="0x43" name="VFMT6_16_16_UNORM"/>
	<value value="0x44" name="VFMT6_16_16_SNORM"/>
	<value value="0x45" name="VFMT6_16_16_FLOAT"/>
	<value value="0x46" name="VFMT6_16_16_UINT"/>
	<value value="0x47" name="VFMT6_16_16_SINT"/>

	<value value="0x48" name="VFMT6_32_UNORM"/>
	<value value="0x49" name="VFMT6_32_SNORM"/>
	<value value="0x4a" name="VFMT6_32_FLOAT"/>
	<value value="0x4b" name="VFMT6_32_UINT"/>
	<value value="0x4c" name="VFMT6_32_SINT"/>
	<value value="0x4d" name="VFMT6_32_FIXED"/>

	<value value="0x58" name="VFMT6_16_16_16_UNORM"/>
	<value value="0x59" name="VFMT6_16_16_16_SNORM"/>
	<value value="0x5a" name="VFMT6_16_16_16_FLOAT"/>
	<value value="0x5b" name="VFMT6_16_16_16_UINT"/>
	<value value="0x5c" name="VFMT6_16_16_16_SINT"/>

	<value value="0x60" name="VFMT6_16_16_16_16_UNORM"/>
	<value value="0x61" name="VFMT6_16_16_16_16_SNORM"/>
	<value value="0x62" name="VFMT6_16_16_16_16_FLOAT"/>
	<value value="0x63" name="VFMT6_16_16_16_16_UINT"/>
	<value value="0x64" name="VFMT6_16_16_16_16_SINT"/>

	<value value="0x65" name="VFMT6_32_32_UNORM"/>
	<value value="0x66" name="VFMT6_32_32_SNORM"/>
	<value value="0x67" name="VFMT6_32_32_FLOAT"/>
	<value value="0x68" name="VFMT6_32_32_UINT"/>
	<value value="0x69" name="VFMT6_32_32_SINT"/>
	<value value="0x6a" name="VFMT6_32_32_FIXED"/>

	<value value="0x70" name="VFMT6_32_32_32_UNORM"/>
	<value value="0x71" name="VFMT6_32_32_32_SNORM"/>
	<value value="0x72" name="VFMT6_32_32_32_UINT"/>
	<value value="0x73" name="VFMT6_32_32_32_SINT"/>
	<value value="0x74" name="VFMT6_32_32_32_FLOAT"/>
	<value value="0x75" name="VFMT6_32_32_32_FIXED"/>

	<value value="0x80" name="VFMT6_32_32_32_32_UNORM"/>
	<value value="0x81" name="VFMT6_32_32_32_32_SNORM"/>
	<value value="0x82" name="VFMT6_32_32_32_32_FLOAT"/>
	<value value="0x83" name="VFMT6_32_32_32_32_UINT"/>
	<value value="0x84" name="VFMT6_32_32_32_32_SINT"/>
	<value value="0x85" name="VFMT6_32_32_32_32_FIXED"/>
</enum>

<enum name="a6xx_tex_fmt">
	<value value="0x02" name="TFMT6_A8_UNORM"/>
	<value value="0x03" name="TFMT6_8_UNORM"/>
	<value value="0x04" name="TFMT6_8_SNORM"/>
	<value value="0x05" name="TFMT6_8_UINT"/>
	<value value="0x06" name="TFMT6_8_SINT"/>
	<value value="0x08" name="TFMT6_4_4_4_4_UNORM"/>
	<value value="0x0a" name="TFMT6_5_5_5_1_UNORM"/>
	<value value="0x0e" name="TFMT6_5_6_5_UNORM"/>
	<value value="0x0f" name="TFMT6_8_8_UNORM"/>
	<value value="0x10" name="TFMT6_8_8_SNORM"/>
	<value value="0x11" name="TFMT6_8_8_UINT"/>
	<value value="0x12" name="TFMT6_8_8_SINT"/>
	<value value="0x13" name="TFMT6_L8_A8_UNORM"/>
	<value value="0x15" name="TFMT6_16_UNORM"/>
	<value value="0x16" name="TFMT6_16_SNORM"/>
	<value value="0x17" name="TFMT6_16_FLOAT"/>
	<value value="0x18" name="TFMT6_16_UINT"/>
	<value value="0x19" name="TFMT6_16_SINT"/>
	<value value="0x30" name="TFMT6_8_8_8_8_UNORM"/>
	<value value="0x31" name="TFMT6_8_8_8_UNORM"/>
	<value value="0x32" name="TFMT6_8_8_8_8_SNORM"/>
	<value value="0x33" name="TFMT6_8_8_8_8_UINT"/>
	<value value="0x34" name="TFMT6_8_8_8_8_SINT"/>
	<value value="0x35" name="TFMT6_9_9_9_E5_FLOAT"/>
	<value value="0x36" name="TFMT6_10_10_10_2_UNORM"/>
	<value value="0x3a" name="TFMT6_10_10_10_2_UINT"/>
	<value value="0x42" name="TFMT6_11_11_10_FLOAT"/>
	<value value="0x43" name="TFMT6_16_16_UNORM"/>
	<value value="0x44" name="TFMT6_16_16_SNORM"/>
	<value value="0x45" name="TFMT6_16_16_FLOAT"/>
	<value value="0x46" name="TFMT6_16_16_UINT"/>
	<value value="0x47" name="TFMT6_16_16_SINT"/>
	<value value="0x4a" name="TFMT6_32_FLOAT"/>
	<value value="0x4b" name="TFMT6_32_UINT"/>
	<value value="0x4c" name="TFMT6_32_SINT"/>
	<value value="0x60" name="TFMT6_16_16_16_16_UNORM"/>
	<value value="0x61" name="TFMT6_16_16_16_16_SNORM"/>
	<value value="0x62" name="TFMT6_16_16_16_16_FLOAT"/>
	<value value="0x63" name="TFMT6_16_16_16_16_UINT"/>
	<value value="0x64" name="TFMT6_16_16_16_16_SINT"/>
	<value value="0x67" name="TFMT6_32_32_FLOAT"/>
	<value value="0x68" name="TFMT6_32_32_UINT"/>
	<value value="0x69" name="TFMT6_32_32_SINT"/>
	<value value="0x72" name="TFMT6_32_32_32_UINT"/>
	<value value="0x73" name="TFMT6_32_32_32_SINT"/>
	<value value="0x74" name="TFMT6_32_32_32_FLOAT"/>
	<value value="0x82" name="TFMT6_32_32_32_32_FLOAT"/>
	<value value="0x83" name="TFMT6_32_32_32_32_UINT"/>
	<value value="0x84" name="TFMT6_32_32_32_32_SINT"/>
	<value value="0x91" name="TFMT6_Z24_UNORM_S8_UINT"/>
	<value value="0xa0" name="TFMT6_X8Z24_UNORM"/>

	<value value="0xab" name="TFMT6_ETC2_RG11_UNORM"/>
	<value value="0xac" name="TFMT6_ETC2_RG11_SNORM"/>
	<value value="0xad" name="TFMT6_ETC2_R11_UNORM"/>
	<value value="0xae" name="TFMT6_ETC2_R11_SNORM"/>
	<value value="0xaf" name="TFMT6_ETC1"/>
	<value value="0xb0" name="TFMT6_ETC2_RGB8"/>
	<value value="0xb1" name="TFMT6_ETC2_RGBA8"/>
	<value value="0xb2" name="TFMT6_ETC2_RGB8A1"/>
	<value value="0xb3" name="TFMT6_DXT1"/>
	<value value="0xb4" name="TFMT6_DXT3"/>
	<value value="0xb5" name="TFMT6_DXT5"/>
	<value value="0xb7" name="TFMT6_RGTC1_UNORM"/>
	<value value="0xb8" name="TFMT6_RGTC1_SNORM"/>
	<value value="0xbb" name="TFMT6_RGTC2_UNORM"/>
	<value value="0xbc" name="TFMT6_RGTC2_SNORM"/>
	<value value="0xbe" name="TFMT6_BPTC_UFLOAT"/>
	<value value="0xbf" name="TFMT6_BPTC_FLOAT"/>
	<value value="0xc0" name="TFMT6_BPTC"/>
	<value value="0xc1" name="TFMT6_ASTC_4x4"/>
	<value value="0xc2" name="TFMT6_ASTC_5x4"/>
	<value value="0xc3" name="TFMT6_ASTC_5x5"/>
	<value value="0xc4" name="TFMT6_ASTC_6x5"/>
	<value value="0xc5" name="TFMT6_ASTC_6x6"/>
	<value value="0xc6" name="TFMT6_ASTC_8x5"/>
	<value value="0xc7" name="TFMT6_ASTC_8x6"/>
	<value value="0xc8" name="TFMT6_ASTC_8x8"/>
	<value value="0xc9" name="TFMT6_ASTC_10x5"/>
	<value value="0xca" name="TFMT6_ASTC_10x6"/>
	<value value="0xcb" name="TFMT6_ASTC_10x8"/>
	<value value="0xcc" name="TFMT6_ASTC_10x10"/>
	<value value="0xcd" name="TFMT6_ASTC_12x10"/>
	<value value="0xce" name="TFMT6_ASTC_12x12"/>
</enum>

<enum name="a6xx_tex_fetchsize">
	<value name="TFETCH6_1_BYTE"  value="0"/>
	<value name="TFETCH6_2_BYTE"  value="1"/>
	<value name="TFETCH6_4_BYTE"  value="2"/>
	<value name="TFETCH6_8_BYTE"  value="3"/>
	<value name="TFETCH6_16_BYTE" value="4"/>
</enum>

<!-- probably same as a5xx -->
<enum name="a6xx_depth_format">
	<value name="DEPTH6_NONE" value="0"/>
	<value name="DEPTH6_16" value="1"/>
	<value name="DEPTH6_24_8" value="2"/>
	<value name="DEPTH6_32" value="4"/>
</enum>

<bitset name="a6x_cp_protect" inline="yes">
	<bitfield name="BASE_ADDR" low="0" high="17"/>
	<bitfield name="MASK_LEN" low="18" high="30"/>
	<bitfield name="READ" pos="31"/>
</bitset>

<enum name="a6xx_shader_id">
	<value value="0x9" name="A6XX_TP0_TMO_DATA"/>
	<value value="0xa" name="A6XX_TP0_SMO_DATA"/>
	<value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
	<value value="0x19" name="A6XX_TP1_TMO_DATA"/>
	<value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
	<value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
	<value value="0x29" name="A6XX_SP_INST_DATA"/>
	<value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
	<value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
	<value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
	<value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
	<value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
	<value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
	<value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
	<value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
	<value value="0x32" name="A6XX_SP_UAV_DATA"/>
	<value value="0x33" name="A6XX_SP_INST_TAG"/>
	<value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
	<value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
	<value value="0x36" name="A6XX_SP_SMO_TAG"/>
	<value value="0x37" name="A6XX_SP_STATE_DATA"/>
	<value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
	<value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
	<value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
	<value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
	<value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
	<value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
	<value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
	<value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
	<value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
	<value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
	<value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
	<value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
	<value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
	<value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
	<value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
	<value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
	<value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
	<value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
	<value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
	<value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
	<value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
	<value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
</enum>

<enum name="a6xx_debugbus_id">
	<value value="0x1" name="A6XX_DBGBUS_CP"/>
	<value value="0x2" name="A6XX_DBGBUS_RBBM"/>
	<value value="0x3" name="A6XX_DBGBUS_VBIF"/>
	<value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
	<value value="0x5" name="A6XX_DBGBUS_UCHE"/>
	<value value="0x6" name="A6XX_DBGBUS_DPM"/>
	<value value="0x7" name="A6XX_DBGBUS_TESS"/>
	<value value="0x8" name="A6XX_DBGBUS_PC"/>
	<value value="0x9" name="A6XX_DBGBUS_VFDP"/>
	<value value="0xa" name="A6XX_DBGBUS_VPC"/>
	<value value="0xb" name="A6XX_DBGBUS_TSE"/>
	<value value="0xc" name="A6XX_DBGBUS_RAS"/>
	<value value="0xd" name="A6XX_DBGBUS_VSC"/>
	<value value="0xe" name="A6XX_DBGBUS_COM"/>
	<value value="0x10" name="A6XX_DBGBUS_LRZ"/>
	<value value="0x11" name="A6XX_DBGBUS_A2D"/>
	<value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
	<value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
	<value value="0x14" name="A6XX_DBGBUS_RBP"/>
	<value value="0x15" name="A6XX_DBGBUS_DCS"/>
	<value value="0x16" name="A6XX_DBGBUS_DBGC"/>
	<value value="0x17" name="A6XX_DBGBUS_CX"/>
	<value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
	<value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
	<value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
	<value value="0x1d" name="A6XX_DBGBUS_GPC"/>
	<value value="0x1e" name="A6XX_DBGBUS_LARC"/>
	<value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
	<value value="0x20" name="A6XX_DBGBUS_RB_0"/>
	<value value="0x21" name="A6XX_DBGBUS_RB_1"/>
	<value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
	<value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
	<value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
	<value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
	<value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
	<value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
	<value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
	<value value="0x40" name="A6XX_DBGBUS_SP_0"/>
	<value value="0x41" name="A6XX_DBGBUS_SP_1"/>
	<value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
	<value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
	<value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
	<value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
</enum>

<enum name="a6xx_cp_perfcounter_select">
	<value value="0" name="PERF_CP_ALWAYS_COUNT"/>
	<value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
	<value value="2" name="PERF_CP_BUSY_CYCLES"/>
	<value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
	<value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
	<value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
	<value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
	<value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
	<value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
	<value value="9" name="PERF_CP_MODE_SWITCH"/>
	<value value="10" name="PERF_CP_ZPASS_DONE"/>
	<value value="11" name="PERF_CP_CONTEXT_DONE"/>
	<value value="12" name="PERF_CP_CACHE_FLUSH"/>
	<value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
	<value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
	<value value="15" name="PERF_CP_SQE_IDLE"/>
	<value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
	<value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
	<value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
	<value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
	<value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
	<value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
	<value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
	<value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
	<value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
	<value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
	<value value="26" name="PERF_CP_SQE_T4_EXEC"/>
	<value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
	<value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
	<value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
	<value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
	<value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
	<value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
	<value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
	<value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
	<value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
	<value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
	<value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
	<value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
	<value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
	<value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
	<value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
	<value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
	<value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
	<value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
	<value value="45" name="PERF_CP_PM4_DATA"/>
	<value value="46" name="PERF_CP_PM4_HEADERS"/>
	<value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
	<value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
	<value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
</enum>

<enum name="a6xx_rbbm_perfcounter_select">
	<value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
	<value value="1" name="PERF_RBBM_ALWAYS_ON"/>
	<value value="2" name="PERF_RBBM_TSE_BUSY"/>
	<value value="3" name="PERF_RBBM_RAS_BUSY"/>
	<value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
	<value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
	<value value="6" name="PERF_RBBM_STATUS_MASKED"/>
	<value value="7" name="PERF_RBBM_COM_BUSY"/>
	<value value="8" name="PERF_RBBM_DCOM_BUSY"/>
	<value value="9" name="PERF_RBBM_VBIF_BUSY"/>
	<value value="10" name="PERF_RBBM_VSC_BUSY"/>
	<value value="11" name="PERF_RBBM_TESS_BUSY"/>
	<value value="12" name="PERF_RBBM_UCHE_BUSY"/>
	<value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
</enum>

<enum name="a6xx_pc_perfcounter_select">
	<value value="0" name="PERF_PC_BUSY_CYCLES"/>
	<value value="1" name="PERF_PC_WORKING_CYCLES"/>
	<value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
	<value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
	<value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
	<value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
	<value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
	<value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
	<value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
	<value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
	<value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
	<value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
	<value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
	<value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
	<value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
	<value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
	<value value="16" name="PERF_PC_INSTANCES"/>
	<value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
	<value value="18" name="PERF_PC_DEAD_PRIM"/>
	<value value="19" name="PERF_PC_LIVE_PRIM"/>
	<value value="20" name="PERF_PC_VERTEX_HITS"/>
	<value value="21" name="PERF_PC_IA_VERTICES"/>
	<value value="22" name="PERF_PC_IA_PRIMITIVES"/>
	<value value="23" name="PERF_PC_GS_PRIMITIVES"/>
	<value value="24" name="PERF_PC_HS_INVOCATIONS"/>
	<value value="25" name="PERF_PC_DS_INVOCATIONS"/>
	<value value="26" name="PERF_PC_VS_INVOCATIONS"/>
	<value value="27" name="PERF_PC_GS_INVOCATIONS"/>
	<value value="28" name="PERF_PC_DS_PRIMITIVES"/>
	<value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
	<value value="30" name="PERF_PC_3D_DRAWCALLS"/>
	<value value="31" name="PERF_PC_2D_DRAWCALLS"/>
	<value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
	<value value="33" name="PERF_TESS_BUSY_CYCLES"/>
	<value value="34" name="PERF_TESS_WORKING_CYCLES"/>
	<value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
	<value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
	<value value="37" name="PERF_PC_TSE_TRANSACTION"/>
	<value value="38" name="PERF_PC_TSE_VERTEX"/>
	<value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
	<value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
	<value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
</enum>

<enum name="a6xx_vfd_perfcounter_select">
	<value value="0" name="PERF_VFD_BUSY_CYCLES"/>
	<value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
	<value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
	<value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
	<value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
	<value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
	<value value="6" name="PERF_VFD_RBUFFER_FULL"/>
	<value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
	<value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
	<value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
	<value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
	<value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
	<value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
	<value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
	<value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
	<value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
	<value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
	<value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
	<value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
	<value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
	<value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
	<value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
	<value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
</enum>

<enum name="a6xx_hlsq_perfcounter_select">
	<value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
	<value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
	<value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
	<value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
	<value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
	<value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
	<value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
	<value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
	<value value="8" name="PERF_HLSQ_QUADS"/>
	<value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
	<value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
	<value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
	<value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
	<value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
	<value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
	<value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
	<value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
	<value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
	<value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
	<value value="19" name="PERF_HLSQ_PIXELS"/>
	<value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
</enum>

<enum name="a6xx_vpc_perfcounter_select">
	<value value="0" name="PERF_VPC_BUSY_CYCLES"/>
	<value value="1" name="PERF_VPC_WORKING_CYCLES"/>
	<value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
	<value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
	<value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
	<value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
	<value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
	<value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
	<value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
	<value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
	<value value="10" name="PERF_VPC_SP_COMPONENTS"/>
	<value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
	<value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
	<value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
	<value value="14" name="PERF_VPC_LM_TRANSACTION"/>
	<value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
	<value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
	<value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
	<value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
	<value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
	<value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
	<value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
	<value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
	<value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
	<value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
	<value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
	<value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
	<value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
</enum>

<enum name="a6xx_tse_perfcounter_select">
	<value value="0" name="PERF_TSE_BUSY_CYCLES"/>
	<value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
	<value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
	<value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
	<value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
	<value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
	<value value="6" name="PERF_TSE_INPUT_PRIM"/>
	<value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
	<value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
	<value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
	<value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
	<value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
	<value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
	<value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
	<value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
	<value value="15" name="PERF_TSE_CINVOCATION"/>
	<value value="16" name="PERF_TSE_CPRIMITIVES"/>
	<value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
	<value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
	<value value="19" name="PERF_TSE_CLIP_PLANES"/>
</enum>

<enum name="a6xx_ras_perfcounter_select">
	<value value="0" name="PERF_RAS_BUSY_CYCLES"/>
	<value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
	<value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
	<value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
	<value value="4" name="PERF_RAS_SUPER_TILES"/>
	<value value="5" name="PERF_RAS_8X4_TILES"/>
	<value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
	<value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
	<value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
	<value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
	<value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
	<value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
	<value value="12" name="PERF_RAS_BLOCKS"/>
</enum>

<enum name="a6xx_uche_perfcounter_select">
	<value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
	<value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
	<value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
	<value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
	<value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
	<value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
	<value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
	<value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
	<value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
	<value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
	<value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
	<value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
	<value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
	<value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
	<value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
	<value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
	<value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
	<value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
	<value value="18" name="PERF_UCHE_EVICTS"/>
	<value value="19" name="PERF_UCHE_BANK_REQ0"/>
	<value value="20" name="PERF_UCHE_BANK_REQ1"/>
	<value value="21" name="PERF_UCHE_BANK_REQ2"/>
	<value value="22" name="PERF_UCHE_BANK_REQ3"/>
	<value value="23" name="PERF_UCHE_BANK_REQ4"/>
	<value value="24" name="PERF_UCHE_BANK_REQ5"/>
	<value value="25" name="PERF_UCHE_BANK_REQ6"/>
	<value value="26" name="PERF_UCHE_BANK_REQ7"/>
	<value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
	<value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
	<value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
	<value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
	<value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
	<value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
	<value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
	<value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
	<value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
	<value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
	<value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
	<value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
	<value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
</enum>

<enum name="a6xx_tp_perfcounter_select">
	<value value="0" name="PERF_TP_BUSY_CYCLES"/>
	<value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
	<value value="2" name="PERF_TP_LATENCY_CYCLES"/>
	<value value="3" name="PERF_TP_LATENCY_TRANS"/>
	<value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
	<value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
	<value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
	<value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
	<value value="8" name="PERF_TP_SP_TP_TRANS"/>
	<value value="9" name="PERF_TP_TP_SP_TRANS"/>
	<value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
	<value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
	<value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
	<value value="13" name="PERF_TP_QUADS_RECEIVED"/>
	<value value="14" name="PERF_TP_QUADS_OFFSET"/>
	<value value="15" name="PERF_TP_QUADS_SHADOW"/>
	<value value="16" name="PERF_TP_QUADS_ARRAY"/>
	<value value="17" name="PERF_TP_QUADS_GRADIENT"/>
	<value value="18" name="PERF_TP_QUADS_1D"/>
	<value value="19" name="PERF_TP_QUADS_2D"/>
	<value value="20" name="PERF_TP_QUADS_BUFFER"/>
	<value value="21" name="PERF_TP_QUADS_3D"/>
	<value value="22" name="PERF_TP_QUADS_CUBE"/>
	<value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
	<value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
	<value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
	<value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
	<value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
	<value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
	<value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
	<value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
	<value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
	<value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
	<value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
	<value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
	<value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
	<value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
	<value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
	<value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
	<value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
	<value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
	<value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
	<value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
	<value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
	<value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
	<value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
	<value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
	<value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
	<value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
	<value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
	<value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
	<value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
	<value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
	<value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
	<value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
	<value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
	<value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
</enum>

<enum name="a6xx_sp_perfcounter_select">
	<value value="0" name="PERF_SP_BUSY_CYCLES"/>
	<value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
	<value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
	<value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
	<value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
	<value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
	<value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
	<value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
	<value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
	<value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
	<value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
	<value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
	<value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
	<value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
	<value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
	<value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
	<value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
	<value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
	<value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
	<value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
	<value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
	<value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
	<value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
	<value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
	<value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
	<value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
	<value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
	<value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
	<value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
	<value value="29" name="PERF_SP_LM_ATOMICS"/>
	<value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
	<value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
	<value value="32" name="PERF_SP_GM_ATOMICS"/>
	<value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
	<value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
	<value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
	<value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
	<value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
	<value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
	<value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
	<value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
	<value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
	<value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
	<value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
	<value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
	<value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
	<value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
	<value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
	<value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
	<value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
	<value value="50" name="PERF_SP_PIXELS_KILLED"/>
	<value value="51" name="PERF_SP_ICL1_REQUESTS"/>
	<value value="52" name="PERF_SP_ICL1_MISSES"/>
	<value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
	<value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
	<value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
	<value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
	<value value="57" name="PERF_SP_GPR_READ"/>
	<value value="58" name="PERF_SP_GPR_WRITE"/>
	<value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
	<value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
	<value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
	<value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
	<value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
	<value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
	<value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
	<value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
	<value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
	<value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
	<value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
	<value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
	<value value="71" name="PERF_SP_WORKING_EU"/>
	<value value="72" name="PERF_SP_ANY_EU_WORKING"/>
	<value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
	<value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
	<value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
	<value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
	<value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
	<value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
	<value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
	<value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
	<value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
	<value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
	<value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
	<value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
</enum>

<enum name="a6xx_rb_perfcounter_select">
	<value value="0" name="PERF_RB_BUSY_CYCLES"/>
	<value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
	<value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
	<value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
	<value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
	<value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
	<value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
	<value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
	<value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
	<value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
	<value value="10" name="PERF_RB_Z_WORKLOAD"/>
	<value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
	<value value="12" name="PERF_RB_Z_READ"/>
	<value value="13" name="PERF_RB_Z_WRITE"/>
	<value value="14" name="PERF_RB_C_READ"/>
	<value value="15" name="PERF_RB_C_WRITE"/>
	<value value="16" name="PERF_RB_TOTAL_PASS"/>
	<value value="17" name="PERF_RB_Z_PASS"/>
	<value value="18" name="PERF_RB_Z_FAIL"/>
	<value value="19" name="PERF_RB_S_FAIL"/>
	<value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
	<value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
	<value value="22" name="PERF_RB_PS_INVOCATIONS"/>
	<value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
	<value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
	<value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
	<value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
	<value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
	<value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
	<value value="29" name="PERF_RB_3D_PIXELS"/>
	<value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
	<value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
	<value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
	<value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
	<value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
	<value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
	<value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
	<value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
	<value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
	<value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
	<value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
	<value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
	<value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
	<value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
	<value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
	<value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
	<value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
	<value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
</enum>

<enum name="a6xx_vsc_perfcounter_select">
	<value value="0" name="PERF_VSC_BUSY_CYCLES"/>
	<value value="1" name="PERF_VSC_WORKING_CYCLES"/>
	<value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
	<value value="3" name="PERF_VSC_EOT_NUM"/>
	<value value="4" name="PERF_VSC_INPUT_TILES"/>
</enum>

<enum name="a6xx_ccu_perfcounter_select">
	<value value="0" name="PERF_CCU_BUSY_CYCLES"/>
	<value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
	<value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
	<value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
	<value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
	<value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
	<value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
	<value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
	<value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
	<value value="9" name="PERF_CCU_GMEM_READ"/>
	<value value="10" name="PERF_CCU_GMEM_WRITE"/>
	<value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
	<value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
	<value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
	<value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
	<value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
	<value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
	<value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
	<value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
	<value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
	<value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
	<value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
	<value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
	<value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
	<value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
	<value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
	<value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
	<value value="27" name="PERF_CCU_2D_RD_REQ"/>
	<value value="28" name="PERF_CCU_2D_WR_REQ"/>
</enum>

<enum name="a6xx_lrz_perfcounter_select">
	<value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
	<value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
	<value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
	<value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
	<value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
	<value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
	<value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
	<value value="7" name="PERF_LRZ_LRZ_READ"/>
	<value value="8" name="PERF_LRZ_LRZ_WRITE"/>
	<value value="9" name="PERF_LRZ_READ_LATENCY"/>
	<value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
	<value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
	<value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
	<value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
	<value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
	<value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
	<value value="16" name="PERF_LRZ_TILE_KILLED"/>
	<value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
	<value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
	<value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
	<value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
	<value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
	<value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
	<value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
	<value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
	<value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
	<value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
	<value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
</enum>

<enum name="a6xx_cmp_perfcounter_select">
	<value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
	<value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
	<value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
	<value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
	<value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
	<value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
	<value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
	<value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
	<value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
	<value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
	<value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
	<value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
	<value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
	<value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
	<value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
	<value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
	<value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
	<value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
	<value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
	<value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
	<value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
	<value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
	<value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
	<value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
	<value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
	<value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
	<value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
	<value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
	<value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
	<value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
	<value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
	<value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
	<value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
	<value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
	<value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
	<value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
	<value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
	<value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
	<value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
	<value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
</enum>

<!--
Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
component type/size, so I think it relates to internal format used for
blending?  The one exception is that 16b unorm and 32b float use the
same value... maybe 16b unorm is uncommon enough that it was just easier
to upconvert to 32b float internally?

 8b unorm:  10
16b unorm:   4

32b int:     7
16b int:     6
 8b int:     5

32b float:   4
16b float:   3
 -->
<enum name="a6xx_2d_ifmt">
	<value value="0x10" name="R2D_UNORM8"/>
	<value value="0x7"  name="R2D_INT32"/>
	<value value="0x6"  name="R2D_INT16"/>
	<value value="0x5"  name="R2D_INT8"/>
	<value value="0x4"  name="R2D_FLOAT32"/>
	<value value="0x3"  name="R2D_FLOAT16"/>
</enum>

<domain name="A6XX" width="32">
	<bitset name="A6XX_RBBM_INT_0_MASK">
		<bitfield name="RBBM_GPU_IDLE" pos="0"/>
		<bitfield name="CP_AHB_ERROR" pos="1"/>
		<bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
		<bitfield name="RBBM_GPC_ERROR" pos="7"/>
		<bitfield name="CP_SW" pos="8"/>
		<bitfield name="CP_HW_ERROR" pos="9"/>
		<bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
		<bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
		<bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
		<bitfield name="CP_IB2" pos="13"/>
		<bitfield name="CP_IB1" pos="14"/>
		<bitfield name="CP_RB" pos="15"/>
		<bitfield name="CP_RB_DONE_TS" pos="17"/>
		<bitfield name="CP_WT_DONE_TS" pos="18"/>
		<bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
		<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
		<bitfield name="RBBM_HANG_DETECT" pos="23"/>
		<bitfield name="UCHE_OOB_ACCESS" pos="24"/>
		<bitfield name="UCHE_TRAP_INTR" pos="25"/>
		<bitfield name="DEBBUS_INTR_0" pos="26"/>
		<bitfield name="DEBBUS_INTR_1" pos="27"/>
		<bitfield name="ISDB_CPU_IRQ" pos="30"/>
		<bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
	</bitset>

	<bitset name="A6XX_CP_INT">
		<bitfield name="CP_OPCODE_ERROR" pos="0"/>
		<bitfield name="CP_UCODE_ERROR" pos="1"/>
		<bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
		<bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
		<bitfield name="CP_AHB_ERROR" pos="5"/>
		<bitfield name="CP_VSD_PARITY_ERROR" pos="6"/>
		<bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/>
	</bitset>

	<reg32 offset="0x0800" name="CP_RB_BASE"/>
	<reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
	<reg32 offset="0x0802" name="CP_RB_CNTL"/>
	<reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
	<reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
	<reg32 offset="0x0806" name="CP_RB_RPTR"/>
	<reg32 offset="0x0807" name="CP_RB_WPTR"/>
	<reg32 offset="0x0808" name="CP_SQE_CNTL"/>
	<reg32 offset="0x0821" name="CP_HW_FAULT"/>
	<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
	<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
	<reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
	<reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
	<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
	<reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1"/>
	<reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2"/>
	<reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
	<reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
	<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/>
	<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
	<reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>

	<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
		<reg32 offset="0x0" name="REG" type="uint"/>
	</array>
	<array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
		<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
	</array>

	<reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
	<reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
	<reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
	<reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
	<reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
	<reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
	<reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
	<reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
	<reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
	<reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
	<reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
	<reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
	<reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
	<reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
	<reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
	<reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
	<reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
	<reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
	<reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
	<reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
	<reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
	<reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
	<reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
	<reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
	<reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
	<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
	<reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
	<reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
	<reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
	<reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
	<reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
	<reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
	<reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
	<reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
	<reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
	<reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
	<reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
	<reg32 offset="0x0928" name="CP_IB1_BASE"/>
	<reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
	<reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
	<reg32 offset="0x092B" name="CP_IB2_BASE"/>
	<reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
	<reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
	<reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
	<reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
	<reg32 offset="0x098D" name="CP_AHB_CNTL"/>
	<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
	<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
	<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/>
	<reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
	<reg32 offset="0x0210" name="RBBM_STATUS">
		<bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" />
		<bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" />
		<bitfield high="21" low="21" name="HLSQ_BUSY" />
		<bitfield high="20" low="20" name="VSC_BUSY" />
		<bitfield high="19" low="19" name="TPL1_BUSY" />
		<bitfield high="18" low="18" name="SP_BUSY" />
		<bitfield high="17" low="17" name="UCHE_BUSY" />
		<bitfield high="16" low="16" name="VPC_BUSY" />
		<bitfield high="15" low="15" name="VFD_BUSY" />
		<bitfield high="14" low="14" name="TESS_BUSY" />
		<bitfield high="13" low="13" name="PC_VSD_BUSY" />
		<bitfield high="12" low="12" name="PC_DCALL_BUSY" />
		<bitfield high="11" low="11" name="COM_DCOM_BUSY" />
		<bitfield high="10" low="10" name="LRZ_BUSY" />
		<bitfield high="9" low="9" name="A2D_BUSY" />
		<bitfield high="8" low="8" name="CCU_BUSY" />
		<bitfield high="7" low="7" name="RB_BUSY" />
		<bitfield high="6" low="6" name="RAS_BUSY" />
		<bitfield high="5" low="5" name="TSE_BUSY" />
		<bitfield high="4" low="4" name="VBIF_BUSY" />
		<bitfield high="3" low="3" name="GFX_DBGC_BUSY" />
		<bitfield high="2" low="2" name="CP_BUSY" />
		<bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
		<bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
	</reg32>
	<reg32 offset="0x0213" name="RBBM_STATUS3"/>
	<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
	<reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
	<reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
	<reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
	<reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
	<reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
	<reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
	<reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
	<reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
	<reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
	<reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
	<reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
	<reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
	<reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
	<reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
	<reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
	<reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
	<reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
	<reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
	<reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
	<reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
	<reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
	<reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
	<reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
	<reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
	<reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
	<reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
	<reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
	<reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
	<reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
	<reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
	<reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
	<reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
	<reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
	<reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
	<reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
	<reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
	<reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
	<reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
	<reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
	<reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
	<reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
	<reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
	<reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
	<reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
	<reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
	<reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
	<reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
	<reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
	<reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
	<reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
	<reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
	<reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
	<reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
	<reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
	<reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
	<reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
	<reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
	<reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
	<reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
	<reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
	<reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
	<reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
	<reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
	<reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
	<reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
	<reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
	<reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
	<reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
	<reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
	<reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
	<reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
	<reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
	<reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
	<reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
	<reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
	<reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
	<reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
	<reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
	<reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
	<reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
	<reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
	<reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
	<reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
	<reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
	<reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
	<reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
	<reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
	<reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
	<reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
	<reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
	<reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
	<reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
	<reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
	<reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
	<reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
	<reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
	<reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
	<reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
	<reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
	<reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
	<reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
	<reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
	<reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
	<reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
	<reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
	<reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
	<reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
	<reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
	<reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
	<reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
	<reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
	<reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
	<reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
	<reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
	<reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
	<reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
	<reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
	<reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
	<reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
	<reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
	<reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
	<reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
	<reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
	<reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
	<reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
	<reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
	<reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
	<reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
	<reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
	<reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
	<reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
	<reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
	<reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
	<reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
	<reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
	<reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
	<reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
	<reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
	<reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
	<reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
	<reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
	<reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
	<reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
	<reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
	<reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
	<reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
	<reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
	<reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
	<reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
	<reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
	<reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
	<reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
	<reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
	<reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
	<reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
	<reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
	<reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
	<reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
	<reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
	<reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
	<reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
	<reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
	<reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
	<reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
	<reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
	<reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
	<reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
	<reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
	<reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
	<reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
	<reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
	<reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
	<reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
	<reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
	<reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
	<reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
	<reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
	<reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
	<reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
	<reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
	<reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
	<reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
	<reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
	<reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
	<reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
	<reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
	<reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
	<reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
	<reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
	<reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
	<reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
	<reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
	<reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
	<reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
	<reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
	<reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
	<reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
	<reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
	<reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
	<reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
	<reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
	<reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
	<reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
	<reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
	<reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
	<reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
	<reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
	<reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
	<reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
	<reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
	<reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
	<reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
	<reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
	<reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
	<reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
	<reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
	<reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
	<reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
	<reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
	<reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
	<reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
	<reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
	<reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
	<reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
	<reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
	<reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
	<reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
	<reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
	<reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
	<reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
	<reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
	<reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
	<reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
	<reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
	<reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
	<reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
	<reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
	<reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
	<reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
	<reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
	<reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
	<reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
	<reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
	<reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
	<reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
	<reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
	<reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
	<reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
	<reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
	<reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
	<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
	<reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
	<reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
	<reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
	<reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
	<reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
	<reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
	<reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
	<reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
	<reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
	<reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
	<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
	<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
	<reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
	<reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
	<reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
	<reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
	<reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
	<reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
	<reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
	<reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
	<reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD"/>
	<reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
	<reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
	<reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
	<reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
	<reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
	<reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
	<reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
	<reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
	<reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
	<reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
	<reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
	<reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
	<reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
	<reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
	<reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
	<reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
	<reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
	<reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
	<reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
	<reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
	<reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
	<reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
	<reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
	<reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
	<reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
	<reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
	<reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
	<reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
	<reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
	<reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
	<reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
	<reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
	<reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
	<reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
	<reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
	<reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
	<reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
	<reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
	<reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
	<reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
	<reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
	<reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
	<reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
	<reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
	<reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
	<reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
	<reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
	<reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
	<reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
	<reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
	<reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
	<reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
	<reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
	<reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
	<reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
	<reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
	<reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
	<reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
	<reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
	<reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
	<reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
	<reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
	<reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
	<reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
	<reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
	<reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
	<reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
	<reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
	<reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
	<reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
	<reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
	<reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
	<reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
	<reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
	<reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
	<reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
	<reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
	<reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
	<reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
	<reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
	<reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
	<reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
	<reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
	<reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
	<reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
	<reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
	<reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
	<reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
	<reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
	<reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
	<reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
	<reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
	<reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
	<reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
	<reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
	<reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
	<reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
	<reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
	<reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
	<reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
	<reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
	<reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
	<reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
	<reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
	<reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
	<reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
	<reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
	<reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
	<reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
	<reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
	<reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
	<reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
	<reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
	<reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
	<reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
	<reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
		<bitfield high="7" low="0" name="PING_INDEX"/>
		<bitfield high="15" low="8" name="PING_BLK_SEL"/>
	</reg32>
	<reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
		<bitfield high="5" low="0" name="TRACEEN"/>
		<bitfield high="14" low="12" name="GRANU"/>
		<bitfield high="31" low="28" name="SEGT"/>
	</reg32>
	<reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
		<bitfield high="27" low="24" name="ENABLE"/>
	</reg32>
	<reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
	<reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
	<reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
	<reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
	<reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
	<reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
	<reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
	<reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
	<reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
		<bitfield high="3" low="0" name="BYTEL0"/>
		<bitfield high="7" low="4" name="BYTEL1"/>
		<bitfield high="11" low="8" name="BYTEL2"/>
		<bitfield high="15" low="12" name="BYTEL3"/>
		<bitfield high="19" low="16" name="BYTEL4"/>
		<bitfield high="23" low="20" name="BYTEL5"/>
		<bitfield high="27" low="24" name="BYTEL6"/>
		<bitfield high="31" low="28" name="BYTEL7"/>
	</reg32>
	<reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
		<bitfield high="3" low="0" name="BYTEL8"/>
		<bitfield high="7" low="4" name="BYTEL9"/>
		<bitfield high="11" low="8" name="BYTEL10"/>
		<bitfield high="15" low="12" name="BYTEL11"/>
		<bitfield high="19" low="16" name="BYTEL12"/>
		<bitfield high="23" low="20" name="BYTEL13"/>
		<bitfield high="27" low="24" name="BYTEL14"/>
		<bitfield high="31" low="28" name="BYTEL15"/>
	</reg32>
	<reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
	<reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
	<reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
	<reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
	<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/>
	<reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
	<reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
	<reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
	<reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
	<reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
	<reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
	<reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
	<reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
	<reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
	<reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
	<reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
	<reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
	<reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/>
	<reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/>
	<reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/>
	<reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/>
	<reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/>
	<reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/>
	<reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/>
	<reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/>
	<reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/>
	<reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/>
	<reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/>
	<reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/>
	<reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/>
	<reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/>
	<reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/>
	<reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/>
	<reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/>
	<reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/>
	<reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/>
	<reg32 offset="0x8E3D" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
	<reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
	<reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
	<reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
	<reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
	<reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
	<reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
	<reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
	<reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
	<reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
	<reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
	<reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
	<reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
	<reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
	<reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
	<reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
	<reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
	<reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
	<reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
	<reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
	<reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
	<reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/>
	<reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
	<reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
	<reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
	<reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
	<reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
	<reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
	<reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
	<reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
	<reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/>
	<reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
	<reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
	<reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
	<reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
	<reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
	<reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
	<reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
	<reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
	<reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
	<reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
	<reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
	<reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
	<reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
	<reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
	<reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
	<reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
	<reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
	<reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
	<reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
	<reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
	<reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
		<bitfield high="7" low="0" name="PERFSEL"/>
	</reg32>
	<reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
	<reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
	<reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
	<reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
	<reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
	<reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
	<reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
	<reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
	<reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
	<reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
	<reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
	<reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
	<reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/>
	<reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
	<reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
	<reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
	<reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
	<reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
	<reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
	<reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
	<reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
	<reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
	<reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
	<reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
	<reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
	<reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
	<reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
	<reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
	<reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
	<reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
	<reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
	<reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
	<reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
	<reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
	<reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
	<reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
	<reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
	<reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
	<reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/>
	<reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
	<reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
	<reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
	<reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
	<reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
	<reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
	<reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
	<reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
	<reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
	<reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
	<reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
	<reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
	<reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
	<reg32 offset="0x3000" name="VBIF_VERSION"/>
	<reg32 offset="0x3001" name="VBIF_CLKON">
		<bitfield pos="1" name="FORCE_ON_TESTBUS"/>
	</reg32>
	<reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
	<reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
	<reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
	<reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
	<reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
	<reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
		<bitfield low="0" high="3" name="DATA_SEL"/>
	</reg32>
	<reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
	<reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
		<bitfield low="0" high="8" name="DATA_SEL"/>
	</reg32>
	<reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
	<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
	<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
	<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
	<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
	<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
	<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
	<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
	<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
	<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
	<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
	<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
	<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
	<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
	<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
	<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
	<reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
	<reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
	<reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
	<reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
	<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
	<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>

	<!-- move/rename these.. -->

	<reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
	<reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
	<reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>

	<!-- same as RB_BIN_CONTROL -->
	<reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
		<bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
		<bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
		<bitfield name="BINNING_PASS" pos="18" type="boolean"/>
		<bitfield name="USE_VIZ" pos="21" type="boolean"/>
	</reg32>

	<!--
		from offset it seems it should be RB, but weird to duplicate
		other regs from same block??
	 -->
	<reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
		<bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
		<bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
	</reg32>

	<reg32 offset="0x0c02" name="VSC_BIN_SIZE">
		<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
		<bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
	</reg32>
	<reg32 offset="0x0c03" name="VSC_SIZE_ADDRESS_LO"/>
	<reg32 offset="0x0c04" name="VSC_SIZE_ADDRESS_HI"/>
	<reg32 offset="0x0c06" name="VSC_BIN_COUNT">
		<bitfield name="NX" low="1" high="10" type="uint"/>
		<bitfield name="NY" low="11" high="20" type="uint"/>
	</reg32>
	<array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
		<reg32 offset="0x0" name="REG">
			<doc>
				Configures the mapping between VSC_PIPE buffer and
				bin, X/Y specify the bin index in the horiz/vert
				direction (0,0 is upper left, 0,1 is leftmost bin
				on second row, and so on).  W/H specify the number
				of bins assigned to this VSC_PIPE in the horiz/vert
				dimension.
			</doc>
			<bitfield name="X" low="0" high="9" type="uint"/>
			<bitfield name="Y" low="10" high="19" type="uint"/>
			<bitfield name="W" low="20" high="25" type="uint"/>
			<bitfield name="H" low="26" high="31" type="uint"/>
		</reg32>
	</array>
	<!--
	compared to a5xx and earlier, we just program the address of the first
	visibility stream and hw adds (pipe_num * VSC_PIPE_DATA_PITCH)

	TODO now there seem to be two buffers of VSC data (both referenced by
	CP_SET_BIN_DATA packet.  Not sure what this new DATA2 one is, but seems
	to have the larger pitch.

	The "DATA2" buffer is probably actually the main visibility stream; it
	is at least the larger of the two.

	For VSC_DATA_PITCH, 0x20 actually seems to be sufficient (although blob
	uses something somewhat larger) for many cases, although required value
	can ramp up somewhat higher.  Values less than 0x20 trigger GPU hangs
	even with small amount of geometry (so possibly 0x20 is minimum
	alignment or something like that).  So far I can't seem to find any-
	thing that needs values larger than 0x20
	 -->
	<reg32 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS_LO"/>
	<reg32 offset="0x0c31" name="VSC_PIPE_DATA2_ADDRESS_HI"/>
	<reg32 offset="0x0c32" name="VSC_PIPE_DATA2_PITCH"/>
	<reg32 offset="0x0c33" name="VSC_PIPE_DATA2_ARRAY_PITCH" shr="4" type="uint"/>
	<reg32 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS_LO"/>
	<reg32 offset="0x0c35" name="VSC_PIPE_DATA_ADDRESS_HI"/>
	<reg32 offset="0x0c36" name="VSC_PIPE_DATA_PITCH"/>
	<reg32 offset="0x0c37" name="VSC_PIPE_DATA_ARRAY_PITCH" shr="4" type="uint"/>

	<array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
		<doc>
			Seems to be a bitmap of which tiles mapped to the VSC
			pipe contain geometry.

			I suppose we can connect a maximum of 32 tiles to a
			single VSC pipe.
		</doc>
		<reg32 offset="0x0" name="REG"/>
	</array>

	<array offset="0x0c58" name="VSC_SIZE2" stride="1" length="32">
		<doc>
			Has the size of data written to corresponding VSC_DATA2
			buffer.
		</doc>
		<reg32 offset="0x0" name="REG"/>
	</array>

	<array offset="0x0c78" name="VSC_SIZE" stride="1" length="32">
		<doc>
			Has the size of data written to corresponding VSC pipe, ie.
			same thing that is written out to VSC_SIZE_ADDRESS_LO/HI
		</doc>
		<reg32 offset="0x0" name="REG"/>
	</array>

	<!-- always 0x03200000 ? -->
	<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>

	<reg32 offset="0x8000" name="GRAS_UNKNOWN_8000"/>
	<reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>

	<!-- always 0x0 ? -->
	<reg32 offset="0x8004" name="GRAS_UNKNOWN_8004"/>

	<reg32 offset="0x8005" name="GRAS_CNTL">
		<!-- see also RB_RENDER_CONTROL0 -->
		<bitfield name="VARYING" pos="0" type="boolean"/>
		<!-- b1 set for interpolateAtCentroid() -->
		<bitfield name="CENTROID" pos="1" type="boolean"/>
		<!-- b2 set instead of b0 when running in per-sample mode -->
		<bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
		<!--
		b3 set for interpolateAt{Offset,Sample}() if not in per-sample
		mode, and frag_face
		 -->
		<bitfield name="SIZE" pos="3" type="boolean"/>
		<!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
		<bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
		<bitfield name="XCOORD" pos="6" type="boolean"/>
		<bitfield name="YCOORD" pos="7" type="boolean"/>
		<bitfield name="ZCOORD" pos="8" type="boolean"/>
		<bitfield name="WCOORD" pos="9" type="boolean"/>
	</reg32>
	<reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
		<bitfield name="HORZ" low="0" high="9" type="uint"/>
		<bitfield name="VERT" low="10" high="19" type="uint"/>
	</reg32>
	<reg32 offset="0x8010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
	<reg32 offset="0x8011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
	<reg32 offset="0x8012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
	<reg32 offset="0x8013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
	<reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
	<reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>

	<reg32 offset="0x8090" name="GRAS_SU_CNTL">
		<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
		<bitfield name="CULL_BACK" pos="1" type="boolean"/>
		<bitfield name="FRONT_CW" pos="2" type="boolean"/>
		<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
		<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
		<bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
		<!-- probably LINEHALFWIDTH is the same as a4xx.. -->
	</reg32>
	<reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
		<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
		<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
	</reg32>
	<reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>

	<reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
		<bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
	</reg32>
	<reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
	<reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
	<reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
	<!-- duplicates RB_DEPTH_BUFFER_INFO: -->
	<reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
	</reg32>

	<!-- always 0x0 -->
	<reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/>

	<!-- always 0x0 ? -->
	<reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>

	<reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>

	<reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
	</reg32>
	<reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
	</reg32>

	<!-- always 0x0 -->
	<reg32 offset="0x80a4" name="GRAS_UNKNOWN_80A4"/>
	<!-- always 0x0 -->
	<reg32 offset="0x80a5" name="GRAS_UNKNOWN_80A5"/>
	<!-- always 0x0 -->
	<reg32 offset="0x80a6" name="GRAS_UNKNOWN_80A6"/>
	<!-- always 0x0 -->
	<reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/>

	<reg32 offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
	<reg32 offset="0x80b1" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
	<reg32 offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
	<reg32 offset="0x80d1" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
	<reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
	<reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>

	<reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
		<!--
		These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
		look when we get around to enabling lrz
		 -->
		<bitfield name="ENABLE" pos="0" type="boolean"/>
		<doc>LRZ write also disabled for blend/etc.</doc>
		<bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
		<doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
		<bitfield name="GREATER" pos="2" type="boolean"/>
		<!-- set at end of batch that had LRZ enabled (to flush/disable it?) -->
		<bitfield name="UNK3" pos="3" type="boolean"/>
		<!-- set when depth-test + depth-write enabled -->
		<bitfield name="UNK4" pos="4" type="boolean"/>
	</reg32>
	<reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/>
	<reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
	</reg32>
	<reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
	<reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
	<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
		<bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/>
		<bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? -->
	</reg32>
	<reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
	<reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>

	<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
		<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
	</reg32>

	<reg32 offset="0x8110" name="GRAS_UNKNOWN_8110"/>

	<enum name="a6xx_rotation">
	  <value value="0x0" name="ROTATE_0"/>
	  <value value="0x1" name="ROTATE_90"/>
	  <value value="0x2" name="ROTATE_180"/>
	  <value value="0x3" name="ROTATE_270"/>
	</enum>

	<bitset name="a6xx_2d_blit_cntl" inline="yes">
		<bitfield name="ROTATE" low="0" high="1" type="a6xx_rotation"/>
		<bitfield name="HORIZONTAL_FLIP" low="2" high="2" type="boolean"/>
		<bitfield name="SOLID_COLOR" low="4" high="4" type="boolean"/>
		<bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_color_fmt"/>
		<bitfield name="SCISSOR" pos="16" type="boolean"/>
		<!-- double check these:
		<bitfield name="FLAGS" pos="18" type="boolean"/>
		<bitfield name="TILE_MODE" low="20" high="21" type="a6xx_tile_mode"/>
		<bitfield name="COLOR_SWAP" low="22" high="23" type="a3xx_color_swap"/>
		-->
		<bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
	</bitset>

	<reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>

	<!-- could be the src coords are fixed point? -->
	<reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X">
		<bitfield name="X" low="8" high="31" type="int"/>
	</reg32>
	<reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X">
		<bitfield name="X" low="8" high="31" type="int"/>
	</reg32>
	<reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y">
		<bitfield name="Y" low="8" high="31" type="int"/>
	</reg32>
	<reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y">
		<bitfield name="Y" low="8" high="31" type="int"/>
	</reg32>

	<reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="adreno_reg_xy"/>
	<reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="adreno_reg_xy"/>

	<reg32 offset="0x840a" name="GRAS_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
	<reg32 offset="0x840b" name="GRAS_RESOLVE_CNTL_2" type="adreno_reg_xy"/>

	<!-- always 0x880 ? -->
	<reg32 offset="0x8600" name="GRAS_UNKNOWN_8600"/>

	<!-- same as GRAS_BIN_CONTROL: -->
	<reg32 offset="0x8800" name="RB_BIN_CONTROL">
		<bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
		<bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
		<bitfield name="BINNING_PASS" pos="18" type="boolean"/>
		<bitfield name="USE_VIZ" pos="21" type="boolean"/>
	</reg32>
	<reg32 offset="0x8801" name="RB_RENDER_CNTL">
		<!-- always set: ?? -->
		<bitfield name="UNK4" pos="4" type="boolean"/>
		<!-- set during binning pass: -->
		<bitfield name="BINNING" pos="7" type="boolean"/>
		<!-- bit seems to be set whenever depth buffer enabled: -->
		<bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
		<!-- bitmask of MRTs using UBWC flag buffer: -->
		<bitfield name="FLAG_MRTS" low="16" high="23"/>
	</reg32>
	<reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
	</reg32>
	<reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
	</reg32>

	<!-- always 0x0 ? -->
	<reg32 offset="0x8804" name="RB_UNKNOWN_8804"/>
	<!-- always 0x0 ? -->
	<reg32 offset="0x8805" name="RB_UNKNOWN_8805"/>
	<!-- always 0x0 ? -->
	<reg32 offset="0x8806" name="RB_UNKNOWN_8806"/>

	<!--
	note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
	name comes from kernel and is probably right)
	 -->
	<reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
		<!-- see also GRAS_CNTL -->
		<bitfield name="VARYING" pos="0" type="boolean"/>
		<!-- b1 set for interpolateAtCentroid() -->
		<bitfield name="CENTROID" pos="1" type="boolean"/>
		<!-- b2 set instead of b0 when running in per-sample mode -->
		<bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
		<!--
		b3 set for interpolateAt{Offset,Sample}() if not in per-sample
		mode, and frag_face
		 -->
		<bitfield name="SIZE" pos="3" type="boolean"/>
		<!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
		<bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
		<bitfield name="XCOORD" pos="6" type="boolean"/>
		<bitfield name="YCOORD" pos="7" type="boolean"/>
		<bitfield name="ZCOORD" pos="8" type="boolean"/>
		<bitfield name="WCOORD" pos="9" type="boolean"/>
		<bitfield name="UNK10" pos="10" type="boolean"/>
	</reg32>
	<reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
		<!-- enable bits for various FS sysvalue regs: -->
		<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
		<bitfield name="FACENESS" pos="2" type="boolean"/>
		<bitfield name="SAMPLEID" pos="3" type="boolean"/>
		<!-- b4 and b5 set in per-sample mode: -->
		<bitfield name="UNK4" pos="4" type="boolean"/>
		<bitfield name="UNK5" pos="5" type="boolean"/>
		<bitfield name="SIZE" pos="6" type="boolean"/>
	</reg32>

	<reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
		<bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
		<bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
	</reg32>
	<reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
		<bitfield name="MRT" low="0" high="3" type="uint"/>
	</reg32>
	<reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
		<bitfield name="RT0" low="0" high="3"/>
		<bitfield name="RT1" low="4" high="7"/>
		<bitfield name="RT2" low="8" high="11"/>
		<bitfield name="RT3" low="12" high="15"/>
		<bitfield name="RT4" low="16" high="19"/>
		<bitfield name="RT5" low="20" high="23"/>
		<bitfield name="RT6" low="24" high="27"/>
		<bitfield name="RT7" low="28" high="31"/>
	</reg32>
	<reg32 offset="0x880e" name="RB_DITHER_CNTL">
		<bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
		<bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>
		<bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>
		<bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>
		<bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>
		<bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
		<bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
		<bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
	</reg32>
	<reg32 offset="0x880f" name="RB_SRGB_CNTL">
		<!-- Same as SP_SRGB_CNTL -->
		<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
		<bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
		<bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
		<bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
		<bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
		<bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
		<bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
		<bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
	</reg32>

	<reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
		<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
	</reg32>
	<reg32 offset="0x8811" name="RB_UNKNOWN_8811"/>

	<!-- always 0x0 ? -->
	<reg32 offset="0x8818" name="RB_UNKNOWN_8818"/>
	<reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
	<reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
	<reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
	<reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
	<reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
	<reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>

	<array offset="0x8820" name="RB_MRT" stride="8" length="8">
		<reg32 offset="0x0" name="CONTROL">
			<bitfield name="BLEND" pos="0" type="boolean"/>
			<bitfield name="BLEND2" pos="1" type="boolean"/>
			<bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
			<bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
			<bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
		</reg32>
		<reg32 offset="0x1" name="BLEND_CONTROL">
			<bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
			<bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
			<bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
			<bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
			<bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
			<bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
		</reg32>
		<reg32 offset="0x2" name="BUF_INFO">
			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
			<bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
			<bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
		</reg32>
		<!--
		at least in gmem, things seem to be aligned to pitch of 64..
		maybe an artifact of tiled format used in gmem?
		 -->
		<reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
		<reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
		<!--
		Compared to a5xx and before, we configure both a GMEM base and
		external base.  Not sure if this is to facilitate GMEM save/
		restore for context switch, or just to simplify state setup to
		not have to care about GMEM vs BYPASS mode.
		 -->
		<reg32 offset="0x5" name="BASE_LO"/>
		<reg32 offset="0x6" name="BASE_HI"/>
		<reg32 offset="0x7" name="BASE_GMEM"/>
	</array>

	<reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
	<reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
	<reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
	<reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
	<reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
		<bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
		<bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
		<bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
	</reg32>
	<reg32 offset="0x8865" name="RB_BLEND_CNTL">
		<!-- per-mrt enable bit -->
		<bitfield name="ENABLE_BLEND" low="0" high="7"/>
		<bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
		<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
		<bitfield name="SAMPLE_MASK" low="16" high="31"/>
	</reg32>
	<reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
		<bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
	</reg32>

	<reg32 offset="0x8871" name="RB_DEPTH_CNTL">
		<bitfield name="Z_ENABLE" pos="0" type="boolean"/>
		<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
		<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
		<doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
		<bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
	</reg32>
	<!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
	<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
	</reg32>
<!-- probably: -->
	<reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
		<doc>stride of depth/stencil buffer</doc>
	</reg32>
	<reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
		<doc>size of layer</doc>
	</reg32>
	<reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
	<reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
	<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>

	<!-- always 0x0 ? -->
	<reg32 offset="0x8878" name="RB_UNKNOWN_8878"/>
	<!-- always 0x0 ? -->
	<reg32 offset="0x8879" name="RB_UNKNOWN_8879"/>

	<reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
		<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
		<bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
		<!--
			set for stencil operations that require read from stencil
			buffer, but not for example for stencil clear (which does
			not require read).. so guessing this is analogous to
			READ_DEST_ENABLE for color buffer..
		 -->
		<bitfield name="STENCIL_READ" pos="2" type="boolean"/>
		<bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
		<bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
		<bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
		<bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
		<bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
		<bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
		<bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
		<bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
	</reg32>
	<reg32 offset="0x8881" name="RB_STENCIL_INFO">
		<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
	</reg32>
	<reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" shr="6" type="uint">
		<doc>stride of stencil buffer</doc>
	</reg32>
	<reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" shr="6" type="uint">
		<doc>size of layer</doc>
	</reg32>
	<reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
	<reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
	<reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/>
	<reg32 offset="0x8887" name="RB_STENCILREF">
		<bitfield name="REF" low="0" high="7"/>
		<bitfield name="BFREF" low="8" high="15"/>
	</reg32>
	<reg32 offset="0x8888" name="RB_STENCILMASK">
		<bitfield name="MASK" low="0" high="7"/>
		<bitfield name="BFMASK" low="8" high="15"/>
	</reg32>
	<reg32 offset="0x8889" name="RB_STENCILWRMASK">
		<bitfield name="WRMASK" low="0" high="7"/>
		<bitfield name="BFWRMASK" low="8" high="15"/>
	</reg32>
	<reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
	<reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
		<bitfield name="COPY" pos="1" type="boolean"/>
	</reg32>

	<reg32 offset="0x8898" name="RB_LRZ_CNTL">
		<bitfield name="ENABLE" pos="0" type="boolean"/>
	</reg32>

	<reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
	<reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
	<reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>

	<reg32 offset="0x88d5" name="RB_MSAA_CNTL">
		<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
	</reg32>
	<reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM"/>
	<!-- s/DST_FORMAT/DST_INFO/ probably: -->
	<reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
		<bitfield name="FLAGS" pos="2" type="boolean"/>
		<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
		<bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_color_fmt"/>
		<bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
	</reg32>
	<reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
	<reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
	<reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
	<!-- array-pitch is size of layer -->
	<reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
	<reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
	<reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
	<reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
		<bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
	</reg32>

	<reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
	<reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
	<reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
	<reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>

	<!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
	<reg32 offset="0x88e3" name="RB_BLIT_INFO">
		<bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
		<bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
		<bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
		<bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
		<doc>
			For clearing depth/stencil
				1 - depth
				2 - stencil
				3 - depth+stencil
			For clearing color buffer:
				then probably a component mask, I always see 0xf
		</doc>
		<bitfield name="CLEAR_MASK" low="4" high="7"/>
	</reg32>

	<!-- always 0x0 ? -->
	<reg32 offset="0x88f0" name="RB_UNKNOWN_88F0"/>

	<reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
	<reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
	<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
		<bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
	</reg32>
	<array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
		<reg32 offset="0" name="ADDR_LO"/>
		<reg32 offset="1" name="ADDR_HI"/>
		<reg32 offset="2" name="PITCH">
			<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
			<bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? -->
		</reg32>
	</array>
	<reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
	<reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>

	<reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
	<reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/>

	<reg32 offset="0x8c17" name="RB_2D_DST_INFO">
		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
		<bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
		<!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
		<bitfield name="FLAGS" pos="12" type="boolean"/>
	</reg32>
	<reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
	<reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
	<reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
		<bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
	</reg32>

	<reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
	<reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
	<reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH">
		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
		<bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
	</reg32>

	<!-- unlike a5xx, these are per channel values rather than packed -->
	<reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
	<reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
	<reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
	<reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>

	<!-- always 0x1 ? -->
	<reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>

	<reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/>

	<reg32 offset="0x8e07" name="RB_CCU_CNTL"/>  <!-- always 7c400004 or 10000000 -->

	<!-- always 0x00ffff00 ? */ -->
	<reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>

	<reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>

	<reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
	<reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/>

	<array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
		<reg32 offset="0x0" name="MODE"/>
	</array>
	<array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
		<reg32 offset="0x0" name="MODE"/>
	</array>

	<!-- always 0x0 -->
	<reg32 offset="0x9210" name="VPC_UNKNOWN_9210"/>
	<reg32 offset="0x9211" name="VPC_UNKNOWN_9211"/>

	<array offset="0x9212" name="VPC_VAR" stride="1" length="4">
		<!-- one bit per varying component: -->
		<reg32 offset="0" name="DISABLE"/>
	</array>

	<reg32 offset="0x9216" name="VPC_SO_CNTL">
		<!-- always 0x10000 when SO enabled.. -->
		<bitfield name="ENABLE" pos="16" type="boolean"/>
	</reg32>
	<reg32 offset="0x9217" name="VPC_SO_PROG">
		<bitfield name="A_BUF" low="0" high="1" type="uint"/>
		<bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
		<bitfield name="A_EN" pos="11" type="boolean"/>
		<bitfield name="B_BUF" low="12" high="13" type="uint"/>
		<bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
		<bitfield name="B_EN" pos="23" type="boolean"/>
	</reg32>
	<array offset="0x921a" name="VPC_SO" stride="7" length="4">
		<reg32 offset="0" name="BUFFER_BASE_LO"/>
		<reg32 offset="1" name="BUFFER_BASE_HI"/>
		<reg32 offset="2" name="BUFFER_SIZE"/>
		<reg32 offset="3" name="NCOMP"/>  <!-- component count -->
		<reg32 offset="4" name="BUFFER_OFFSET"/>
		<reg32 offset="5" name="FLUSH_BASE_LO"/>
		<reg32 offset="6" name="FLUSH_BASE_HI"/>
	</array>

	<!-- always 0x0 ? -->
	<reg32 offset="0x9236" name="VPC_UNKNOWN_9236">
		<bitfield name="POINT_COORD_INVERT" pos="0" type="uint"/>
	</reg32>

	<!-- always 0x0 ? -->
	<reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/>

	<reg32 offset="0x9301" name="VPC_PACK">
		<doc>
			num of varyings plus four for gl_Position (plus one if gl_PointSize)
			plus # of transform-feedback (streamout) varyings if using the
			hw streamout (rather than stg instructions in shader)
		</doc>
		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
		<bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/>
		<!--
		This seems to be the OUTLOC for the psize output.  It could possibly
		be the max-OUTLOC position, but it is only set when VS writes psize
		(and blob always puts psize at highest OUTLOC)
		 -->
		<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
	</reg32>

	<reg32 offset="0x9303" name="VPC_PACK_3">
		<doc>
		  domain shader version

			num of varyings plus four for gl_Position (plus one if gl_PointSize)
			plus # of transform-feedback (streamout) varyings if using the
			hw streamout (rather than stg instructions in shader)
		</doc>
		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
		<bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/>
		<!--
		This seems to be the OUTLOC for the psize output.  It could possibly
		be the max-OUTLOC position, but it is only set when VS writes psize
		(and blob always puts psize at highest OUTLOC)
		 -->
		<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
	</reg32>

	<reg32 offset="0x9304" name="VPC_CNTL_0">
		<bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
		<bitfield name="VARYING" pos="16" type="boolean"/>
	</reg32>

	<reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
		<bitfield name="BUF0" pos="0" type="boolean"/>
		<bitfield name="BUF1" pos="3" type="boolean"/>
		<bitfield name="BUF2" pos="6" type="boolean"/>
		<bitfield name="BUF3" pos="9" type="boolean"/>
		<bitfield name="ENABLE" pos="15" type="boolean"/>
	</reg32>
	<reg32 offset="0x9306" name="VPC_SO_OVERRIDE">
		<bitfield name="SO_DISABLE" pos="0" type="boolean"/>
	</reg32>

	<!-- always 0x0 ? -->
	<reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/>
	<!-- always 0x0 ? -->
	<reg32 offset="0x9602" name="VPC_UNKNOWN_9602"/>

	<reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/>

	<!-- always 0x0 ? -->
	<reg32 offset="0x9801" name="PC_UNKNOWN_9801"/>

	<enum name="a6xx_tess_spacing">
	  <value value="0x0" name="TESS_EQUAL"/>
	  <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
	  <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
	</enum>

	<reg32 offset="0x9802" name="PC_TESS_CNTL">
	  <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
	  <bitfield name="CCW" pos="2" type="boolean"/>
	  <bitfield name="PRIMITIVES" pos="3" type="boolean"/>
	</reg32>

	<!-- probably: -->
	<reg32 offset="0x9803" name="PC_RESTART_INDEX"/>
	<reg32 offset="0x9804" name="PC_MODE_CNTL"/>

	<!-- always 0x1 ? -->
	<reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
	<reg32 offset="0x9806" name="PC_UNKNOWN_9806"/>

	<reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
	<reg32 offset="0x9981" name="PC_UNKNOWN_9981"/>

	<reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>

	<reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
		<bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
		<!-- maybe?  b1 seems always set, so just assume it is for now: -->
		<bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
	</reg32>
	<reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1">
		<doc>
		        vertex shader

			num of varyings plus four for gl_Position (plus one if gl_PointSize)
			plus # of transform-feedback (streamout) varyings if using the
			hw streamout (rather than stg instructions in shader)
		</doc>
		<bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
		<bitfield name="PSIZE" pos="8" type="boolean"/>
	</reg32>

	<reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
		<doc>
		        hull shader?

			num of varyings plus four for gl_Position (plus one if gl_PointSize)
			plus # of transform-feedback (streamout) varyings if using the
			hw streamout (rather than stg instructions in shader)
		</doc>
		<bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
		<bitfield name="PSIZE" pos="8" type="boolean"/>
	</reg32>
	<reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4">
		<doc>
		        domain shader
			num of varyings plus four for gl_Position (plus one if gl_PointSize)
			plus # of transform-feedback (streamout) varyings if using the
			hw streamout (rather than stg instructions in shader)
		</doc>
		<bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
		<bitfield name="PSIZE" pos="8" type="boolean"/>
	</reg32>

	<!-- always 0x0 ? -->
	<reg32 offset="0x9b06" name="PC_UNKNOWN_9B06"/>
	<reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>

	<reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
	<reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>

	<!-- always 0x0 -->
	<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>

	<reg32 offset="0xa000" name="VFD_CONTROL_0">
		<bitfield name="VTXCNT" low="0" high="5" type="uint"/>
	</reg32>
	<reg32 offset="0xa001" name="VFD_CONTROL_1">
		<bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
		<bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
		<bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
	</reg32>
	<reg32 offset="0xa002" name="VFD_CONTROL_2">
		<bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
		<bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
	</reg32>
	<reg32 offset="0xa003" name="VFD_CONTROL_3">
		<bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
		<bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
		<bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
	</reg32>
	<reg32 offset="0xa004" name="VFD_CONTROL_4">
	</reg32>
	<reg32 offset="0xa005" name="VFD_CONTROL_5">
	</reg32>
	<reg32 offset="0xa006" name="VFD_CONTROL_6">
	</reg32>

	<reg32 offset="0xa007" name="VFD_MODE_CNTL">
		<bitfield name="BINNING_PASS" pos="0" type="boolean"/>
	</reg32>

	<!-- always 0x0 ? -->
	<reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/>
	<reg32 offset="0xa009" name="VFD_UNKNOWN_A009"/>

	<reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
	<reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
	<array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
		<reg32 offset="0x0" name="BASE_LO"/>
		<reg32 offset="0x1" name="BASE_HI"/>
		<reg32 offset="0x2" name="SIZE" type="uint"/>
		<reg32 offset="0x3" name="STRIDE" type="uint"/>
	</array>
	<array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
		<reg32 offset="0x0" name="INSTR">
			<!-- IDX appears to index into VFD_FETCH[] -->
			<bitfield name="IDX" low="0" high="4" type="uint"/>
			<bitfield name="INSTANCED" pos="17" type="boolean"/>
			<bitfield name="FORMAT" low="20" high="27" type="a6xx_vtx_fmt"/>
			<bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
			<bitfield name="UNK30" pos="30" type="boolean"/>
			<bitfield name="FLOAT" pos="31" type="boolean"/>
		</reg32>
		<reg32 offset="0x1" name="STEP_RATE"/>
	</array>
	<array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
		<reg32 offset="0x0" name="INSTR">
			<bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
			<bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
		</reg32>
	</array>

	<!-- always 0x1 ? -->
	<reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>

	<reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
		<!-- # of VS outputs including pos/psize -->
		<bitfield name="VSOUT" low="0" high="4" type="uint"/>
	</reg32>
	<array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
		<reg32 offset="0x0" name="REG">
			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
		</reg32>
	</array>
	<!--
	Starting with a5xx, position/psize outputs from shader end up in the
	SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
	the last entries too, except when gl_PointCoord is used, blob inserts
	an extra varying after, but with a lower OUTLOC position.  If present,
	psize is last, preceded by position.
	 -->
	<array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
		<reg32 offset="0x0" name="REG">
			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
		</reg32>
	</array>

	<bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
		<!--
		When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
		used registers is a bit odd too:
			- used (half): 0-15 68-179 (cnt=128, max=179)
			- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
		whereas we usually see a (mostly) contiguous range of regs used.  But if
		I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
		then:
			- used (merged): 0-191 (cnt=192, max=191)
		So I think if b31 is set, then the half precision registers overlap
		the full precision registers.  (Which seems like a pretty sensible
		feature, actually I'm not sure when you *wouldn't* want to use that,
		since it gives register allocation more flexibility)
		 -->
		<bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
		<bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
		<!-- seems to be nesting level for flow control:.. -->
		<bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
		<bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
		<bitfield name="VARYING" pos="22" type="boolean"/>
		<bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
		<bitfield name="MERGEDREGS" pos="31" type="boolean"/>
	</bitset>

	<bitset name="a6xx_sp_xs_config" inline="yes">
		<bitfield name="ENABLED" pos="8" type="boolean"/>
		<!--
		number of textures and samplers.. these might be swapped, with GL I
		always see the same value for both.
		 -->
		<bitfield name="NTEX" low="9" high="16" type="uint"/>
		<bitfield name="NSAMP" low="17" high="21" type="uint"/>
		<bitfield name="NIBO" low="22" high="29" type="uint"/>
	</bitset>

	<reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
	<reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
	<reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
	<reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
	<reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/>
	<reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
	<reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/>

	<reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
	<reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/>
	<reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/>
	<reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
	<reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
	<reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/>
	<reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
	<reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/>

	<reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
	<reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
		<!-- # of DS outputs including pos/psize -->
		<bitfield name="DSOUT" low="0" high="4" type="uint"/>
	</reg32>
	<array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
		<reg32 offset="0x0" name="REG">
			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
		</reg32>
	</array>
	<array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
		<reg32 offset="0x0" name="REG">
			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
		</reg32>
	</array>

	<reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/>
	<reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
	<reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
	<reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/>
	<reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
	<reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/>

	<reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
	<reg32 offset="0xa871" name="SP_GS_UNKNOWN_A871"/>
	<reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
	<reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
	<reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
	<reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
	<reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>

	<reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
	<reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
	<reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
	<reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
	<reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
	<reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
	<reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
	<reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
	<reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
	<reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
	<reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
	<reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
	<reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
	<reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
	<reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
	<reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>

	<reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
	<reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
	<reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
	<reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>

	<reg32 offset="0xa989" name="SP_BLEND_CNTL">
		<bitfield name="ENABLED" pos="0" type="boolean"/>
		<bitfield name="UNK8" pos="8" type="boolean"/>
		<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
	</reg32>
	<reg32 offset="0xa98a" name="SP_SRGB_CNTL">
		<!-- Same as RB_SRGB_CNTL -->
		<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
		<bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
		<bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
		<bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
		<bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
		<bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
		<bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
		<bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
	</reg32>
	<reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
		<bitfield name="RT0" low="0" high="3"/>
		<bitfield name="RT1" low="4" high="7"/>
		<bitfield name="RT2" low="8" high="11"/>
		<bitfield name="RT3" low="12" high="15"/>
		<bitfield name="RT4" low="16" high="19"/>
		<bitfield name="RT5" low="20" high="23"/>
		<bitfield name="RT6" low="24" high="27"/>
		<bitfield name="RT7" low="28" high="31"/>
	</reg32>
	<reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
		<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
		<bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
	</reg32>
	<reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
		<bitfield name="MRT" low="0" high="3" type="uint"/>
	</reg32>

	<array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
		<reg32 offset="0" name="REG">
			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
			<bitfield name="COLOR_SINT" pos="8" type="boolean"/>
			<bitfield name="COLOR_UINT" pos="9" type="boolean"/>
		</reg32>
	</array>

	<reg32 offset="0xa99e" name="SP_UNKNOWN_A99E"/>

	<reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>

	<!-- always 0x0 ? -->
	<reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>

	<!-- set for compute shaders, always 0x41 -->
	<reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint"/>

	<!-- set for compute shaders, always 0x0 -->
	<reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>

	<reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>

	<reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
	<reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
	<reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
	<reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
	<reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
	<reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
	<reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
	<reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>

	<array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
		<doc>per MRT</doc>
		<reg32 offset="0x0" name="REG">
			<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
			<bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
		</reg32>
	</array>

	<reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
	<reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
	<reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
	<reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
	<reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/>

	<!--
	IBO state for compute shader:
	 -->
	<reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
	<reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
	<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>

	<!-- always 0x5 ? -->
	<reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>

	<reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
	<reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>

	<!--
	Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
	instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.
	 -->
	<reg32 offset="0xab1a" name="SP_IBO_LO"/>
	<reg32 offset="0xab1b" name="SP_IBO_HI"/>
	<reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>

	<!--
	I believe this describes the src format, but haven't seen traces with
	src_format != dst_format
	 -->
	<reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT">
		<bitfield name="NORM" pos="0" type="boolean"/>
		<bitfield name="SINT" pos="1" type="boolean"/>
		<bitfield name="UINT" pos="2" type="boolean"/>
		<bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_color_fmt"/>
	</reg32>

	<!-- always 0x0 -->
	<reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>

	<reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
	<reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>

	<!-- always 0x3f ? -->
	<reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>

	<!-- always 0x0 ? -->
	<reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
	<reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>

	<!-- could be all the stuff below here is actually TPL1?? -->

	<reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
	</reg32>
	<reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
		<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
	</reg32>

	<!-- looks to work in the same way as a5xx: -->
	<reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
	<reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
	<!-- always 0x0 ? -->
	<reg32 offset="0xb304" name="SP_TP_UNKNOWN_B304"/>

	<reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>

	<!--
	Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
	badly named or the functionality moved in a6xx.  But downstream kernel
	calls this "a6xx_sp_ps_tp_2d_cluster"
	 -->
	<reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO">
		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
		<bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
		<!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
		<bitfield name="FLAGS" pos="12" type="boolean"/>
		<bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
		<bitfield name="FILTER" pos="16" type="boolean"/>
	</reg32>
	<reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
	</reg32>
	<reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
	<reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
	<reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
	   <bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
	</reg32>

	<reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
	<reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
	<reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
		<bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
	</reg32>

	<!-- always 0x00100000 ? -->
	<reg32 offset="0xb600" name="SP_UNKNOWN_B600"/>

	<!-- always 0x44 ? -->
	<reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>

	<bitset name="a6xx_hlsq_xs_cntl" inline="yes">
		<bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
		<bitfield name="ENABLED" pos="8" type="boolean"/>
	</bitset>

	<reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
	<reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
	<reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
	<reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>

	<reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/>

	<reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG">
		<!-- always 0x7 ? -->
	</reg32>
	<reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
		<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
		<!-- SAMPLEID is loaded into a half-precision register: -->
		<bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
		<bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
		<!--
		SIZE is the "size" of the primitive, ie. what the i/j coords need
		to be divided by to scale to a single fragment.  It is probably
		the longer of the two lines that form the tri (ie v0v1 and v0v2)?
		 -->
		<bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
	</reg32>
	<reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
		<!-- register loaded with position (bary.f) -->
		<bitfield name="BARY_IJ_PIXEL" low="0" high="7" type="a3xx_regid"/>
		<bitfield name="BARY_IJ_CENTROID" low="16" high="23" type="a3xx_regid"/>
	</reg32>
	<reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
		<bitfield name="BARY_IJ_PIXEL_PERSAMP" low="0" high="7" type="a3xx_regid"/>
		<bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
		<bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
	</reg32>
	<reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
		<!-- unknown regid in low 8b -->
	</reg32>
	<reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>

	<reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
		<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
		<!-- localsize is value minus one: -->
		<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
		<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
		<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
	</reg32>
	<reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
		<bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
	</reg32>
	<reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
		<bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
	</reg32>
	<reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
		<bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
	</reg32>
	<reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
		<bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
	</reg32>
	<reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
		<bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
	</reg32>
	<reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
		<bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
	</reg32>
	<reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
		<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
		<bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
		<bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
		<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
	</reg32>
	<reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
	<reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
	<reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
	<reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>

	<!-- probably: -->
	<reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/>

	<reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>

	<!-- always 0x0 ? -->
	<reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/>

	<!-- always 0x80 ? -->
	<reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
	<!-- always 0x0 ? -->
	<reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
	<!-- always 0x0 ? -->
	<reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>

</domain>

<!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
<domain name="A6XX_TEX_SAMP" width="32">
	<doc>Texture sampler dwords</doc>
	<enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
		<value name="A6XX_TEX_NEAREST" value="0"/>
		<value name="A6XX_TEX_LINEAR" value="1"/>
		<value name="A6XX_TEX_ANISO" value="2"/>
	</enum>
	<enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
		<value name="A6XX_TEX_REPEAT" value="0"/>
		<value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
		<value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
		<value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
		<value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
	</enum>
	<enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
		<value name="A6XX_TEX_ANISO_1" value="0"/>
		<value name="A6XX_TEX_ANISO_2" value="1"/>
		<value name="A6XX_TEX_ANISO_4" value="2"/>
		<value name="A6XX_TEX_ANISO_8" value="3"/>
		<value name="A6XX_TEX_ANISO_16" value="4"/>
	</enum>
	<reg32 offset="0" name="0">
		<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
		<bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
		<bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
		<bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
		<bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
		<bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
		<bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
		<bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
	</reg32>
	<reg32 offset="1" name="1">
		<bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
		<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
		<bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
		<bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
		<bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
		<bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
	</reg32>
	<reg32 offset="2" name="2">
		<bitfield name="BCOLOR_OFFSET" low="0" high="31"/>
	</reg32>
	<reg32 offset="3" name="3"/>
</domain>

<domain name="A6XX_TEX_CONST" width="32">
	<doc>Texture constant dwords</doc>
	<enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
		<value name="A6XX_TEX_X" value="0"/>
		<value name="A6XX_TEX_Y" value="1"/>
		<value name="A6XX_TEX_Z" value="2"/>
		<value name="A6XX_TEX_W" value="3"/>
		<value name="A6XX_TEX_ZERO" value="4"/>
		<value name="A6XX_TEX_ONE" value="5"/>
	</enum>
	<enum name="a6xx_tex_type"> <!-- same as a4xx? -->
		<value name="A6XX_TEX_1D" value="0"/>
		<value name="A6XX_TEX_2D" value="1"/>
		<value name="A6XX_TEX_CUBE" value="2"/>
		<value name="A6XX_TEX_3D" value="3"/>
	</enum>
	<reg32 offset="0" name="0">
		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
		<bitfield name="SRGB" pos="2" type="boolean"/>
		<bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
		<bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
		<bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
		<bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
		<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
		<bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
		<bitfield name="FMT" low="22" high="29" type="a6xx_tex_fmt"/>
		<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
	</reg32>
	<reg32 offset="1" name="1">
		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
	</reg32>
	<reg32 offset="2" name="2">
		<!--
		b4 and b31 set for buffer/ssbo case, in which case low 15 bits
		of size encoded in WIDTH, and high 15 bits encoded in HEIGHT

		b31 is probably the 'BUFFER' bit.. it is the one that changes
		behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
		 -->
		<bitfield name="UNK4" pos="4" type="boolean"/>
		<bitfield name="FETCHSIZE" low="0" high="3" type="a6xx_tex_fetchsize"/>
		<doc>Pitch in bytes (so actually stride)</doc>
		<bitfield name="PITCH" low="7" high="28" type="uint"/>
		<bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
		<bitfield name="UNK31" pos="31" type="boolean"/>
	</reg32>
	<reg32 offset="3" name="3">
		<!--
		ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
		for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
		layer size at the point that it stops being reduced moving to
		higher (smaller) mipmap levels
		 -->
		<bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
		<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
		<bitfield name="UNK27" pos="27" type="boolean"/>
		<bitfield name="FLAG" pos="28" type="boolean"/>
	</reg32>
	<reg32 offset="4" name="4">
		<bitfield name="BASE_LO" low="5" high="31" shr="5"/>
	</reg32>
	<reg32 offset="5" name="5">
		<bitfield name="BASE_HI" low="0" high="16"/>
		<bitfield name="DEPTH" low="17" high="29" type="uint"/>
	</reg32>
	<reg32 offset="6" name="6"/>
	<reg32 offset="7" name="7">
		<bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
	</reg32>
	<reg32 offset="8" name="8">
		<bitfield name="FLAG_HI" low="0" high="16"/>
	</reg32>
	<reg32 offset="9" name="9">
		<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
	</reg32>
	<reg32 offset="10" name="10">
		<!--
		I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
		don't seem to be particularly sensible... or needed for UBWC to work
		 -->
		<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
	</reg32>
	<reg32 offset="11" name="11"/>
	<reg32 offset="12" name="12"/>
	<reg32 offset="13" name="13"/>
	<reg32 offset="14" name="14"/>
	<reg32 offset="15" name="15"/>
</domain>

<!--
Note the "SSBO" state blocks are actually used for both images and SSBOs,
naming is just because I r/e'd SSBOs first.  I should probably come up
with a better name.
-->
<domain name="A6XX_IBO" width="32">
	<reg32 offset="0" name="0">
		<!--
		NOTE: same position as in TEX_CONST state.. I don't see other bits
		used but if they are good chance position is same as TEX_CONST
		 -->
		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
		<bitfield name="FMT" low="22" high="29" type="a6xx_tex_fmt"/>
	</reg32>
	<reg32 offset="1" name="1">
		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
	</reg32>
	<reg32 offset="2" name="2">
		<!--
		b4 and b31 set for buffer/ssbo case, in which case low 15 bits
		of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
		 -->
		<bitfield name="UNK4" pos="4" type="boolean"/>
		<doc>Pitch in bytes (so actually stride)</doc>
		<bitfield name="PITCH" low="7" high="28" type="uint"/>
		<bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
		<bitfield name="UNK31" pos="31" type="boolean"/>
	</reg32>
	<reg32 offset="3" name="3">
		<!--
		ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
		for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
		layer size at the point that it stops being reduced moving to
		higher (smaller) mipmap levels
		 -->
		<bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
		<bitfield name="UNK27" pos="27" type="boolean"/>
		<bitfield name="FLAG" pos="28" type="boolean"/>
	</reg32>
	<reg32 offset="4" name="4">
		<bitfield name="BASE_LO" low="0" high="31"/>
	</reg32>
	<reg32 offset="5" name="5">
		<bitfield name="BASE_HI" low="0" high="16"/>
		<bitfield name="DEPTH" low="17" high="29" type="uint"/>
	</reg32>
	<reg32 offset="6" name="6">
	</reg32>
	<reg32 offset="7" name="7">
	</reg32>
	<reg32 offset="8" name="8">
	</reg32>
	<reg32 offset="9" name="9">
		<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
	</reg32>
	<reg32 offset="10" name="10">
		<!--
		I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
		don't seem to be particularly sensible... or needed for UBWC to work
		 -->
		<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
	</reg32>
</domain>

<domain name="A6XX_UBO" width="32">
	<reg32 offset="0" name="0">
		<bitfield name="BASE_LO" low="0" high="31"/>
	</reg32>
	<reg32 offset="1" name="1">
		<bitfield name="BASE_HI" low="0" high="16"/>
		<!-- size probably in high bits -->
	</reg32>
</domain>

<domain name="CP_UNK_A6XX_55" width="32">
	<reg32 offset="0" name="0">
		<bitfield name="BASE_LO" low="0" high="31"/>
	</reg32>
	<reg32 offset="1" name="1">
		<bitfield name="BASE_HI" low="0" high="16"/>
	</reg32>
	<reg32 offset="2" name="2">
		<bitfield name="SIZE" low="0" high="15"/>
	</reg32>
</domain>

<domain name="A6XX_PDC" width="32">
	<reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
	<reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
	<reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
	<reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
	<reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
	<reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
	<reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
	<reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
	<reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
	<reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
	<reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
	<reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
	<reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
	<reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
	<reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
	<reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
	<reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
	<reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
	<reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
	<reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
	<reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
	<reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
	<reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
	<reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
	<reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
	<reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
</domain>

<domain name="A6XX_PDC_GPU_SEQ" width="32">
	<reg32 offset="0x0" name="MEM_0"/>
</domain>

<domain name="A6XX_CX_DBGC" width="32">
	<reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
		<bitfield high="7" low="0" name="PING_INDEX"/>
		<bitfield high="15" low="8" name="PING_BLK_SEL"/>
	</reg32>
	<reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
	<reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
	<reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
	<reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
		<bitfield high="5" low="0" name="TRACEEN"/>
		<bitfield high="14" low="12" name="GRANU"/>
		<bitfield high="31" low="28" name="SEGT"/>
	</reg32>
	<reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
		<bitfield high="27" low="24" name="ENABLE"/>
	</reg32>
	<reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
	<reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
	<reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
	<reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
	<reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
	<reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
	<reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
	<reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
	<reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
		<bitfield high="3" low="0" name="BYTEL0"/>
		<bitfield high="7" low="4" name="BYTEL1"/>
		<bitfield high="11" low="8" name="BYTEL2"/>
		<bitfield high="15" low="12" name="BYTEL3"/>
		<bitfield high="19" low="16" name="BYTEL4"/>
		<bitfield high="23" low="20" name="BYTEL5"/>
		<bitfield high="27" low="24" name="BYTEL6"/>
		<bitfield high="31" low="28" name="BYTEL7"/>
	</reg32>
	<reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
		<bitfield high="3" low="0" name="BYTEL8"/>
		<bitfield high="7" low="4" name="BYTEL9"/>
		<bitfield high="11" low="8" name="BYTEL10"/>
		<bitfield high="15" low="12" name="BYTEL11"/>
		<bitfield high="19" low="16" name="BYTEL12"/>
		<bitfield high="23" low="20" name="BYTEL13"/>
		<bitfield high="27" low="24" name="BYTEL14"/>
		<bitfield high="31" low="28" name="BYTEL15"/>
	</reg32>

	<reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
	<reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
</domain>

<domain name="A6XX_CX_MISC" width="32">
	<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
	<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
</domain>

</database>