intel: Fix aux map alignments on 32-bit builds.
ALIGN() brilliantly uses uintptr_t, making it unsafe for use with 64-bit
GPU addresses in 32-bit builds of the driver. Use align64() instead,
which uses uint64_t.
Fixes assertion failures when running any 32-bit program on Tigerlake.
Fixes: 2e6a7ced4db ("iris/gen12: Write GFX_AUX_TABLE base address register")
Fixes: 0d0290bb3f7 ("intel/common: Add surface to aux map translation table support")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3507>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3507>
(cherry picked from commit 8dc0540a171627cb502f76c75a29a43a86328a95)
diff --git a/.pick_status.json b/.pick_status.json
index b52ef29..b4c3d70 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -904,7 +904,7 @@
"description": "intel: Fix aux map alignments on 32-bit builds.",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"master_sha": null,
"because_sha": "2e6a7ced4dbc70149280fe3c8c453a228c73c524"
},
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index f6f4a7f..d266c9f 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -5023,7 +5023,7 @@
* cached translations.
*/
uint64_t base_addr = gen_aux_map_get_base(aux_map_ctx);
- assert(base_addr != 0 && ALIGN(base_addr, 32 * 1024) == base_addr);
+ assert(base_addr != 0 && align64(base_addr, 32 * 1024) == base_addr);
iris_load_register_imm64(batch, GENX(GFX_AUX_TABLE_BASE_ADDR_num),
base_addr);
batch->last_aux_map_state = aux_map_state_num;
diff --git a/src/intel/common/gen_aux_map.c b/src/intel/common/gen_aux_map.c
index 398f024..eb9dda8 100644
--- a/src/intel/common/gen_aux_map.c
+++ b/src/intel/common/gen_aux_map.c
@@ -151,7 +151,7 @@
struct aux_map_buffer *tail =
list_last_entry(&ctx->buffers, struct aux_map_buffer, link);
uint64_t gpu = tail->buffer->gpu + ctx->tail_offset;
- uint64_t aligned = ALIGN(gpu, align);
+ uint64_t aligned = align64(gpu, align);
if ((aligned - gpu) + size > ctx->tail_remaining) {
return false;
@@ -464,8 +464,8 @@
pthread_mutex_lock(&ctx->mutex);
uint64_t map_addr = address;
uint64_t dest_aux_addr = aux_address;
- assert(ALIGN(address, 64 * 1024) == address);
- assert(ALIGN(aux_address, 4 * 64) == aux_address);
+ assert(align64(address, 64 * 1024) == address);
+ assert(align64(aux_address, 4 * 64) == aux_address);
while (map_addr - address < isl_surf->size_B) {
add_mapping(ctx, map_addr, dest_aux_addr, isl_surf, &state_changed);
map_addr += 64 * 1024;
@@ -540,7 +540,7 @@
address + size);
uint64_t map_addr = address;
- assert(ALIGN(address, 64 * 1024) == address);
+ assert(align64(address, 64 * 1024) == address);
while (map_addr - address < size) {
remove_mapping(ctx, map_addr, &state_changed);
map_addr += 64 * 1024;