blob: a922b5905e5b8c92c28cd3a6c0543c8a749c3894 [file] [log] [blame]
Initial placement cost = 786.354
Cost recomputed from scratch is 255.033325.
Final Placement cost: 255.041
VPR FPGA Placement and Routing Program Version 4.00-spec
Source completed August 19, 1997.
General Options:
The circuit will be placed but not routed.
Placer Options:
User annealing schedule selected with:
Initial Temperature: 5
Exit (Final) Temperature: 0.005
Temperature Reduction factor (alpha_t): 0.9412
Number of moves in the inner loop is (num_blocks)^4/3 * 2
Placement cost type is linear congestion.
Placement will be performed once.
Placement channel width factor = 100.
Exponent used in placement cost: 1
Initial random seed: 1
Reading the FPGA architectural description from
Successfully read
Pins per clb: 6. Pads per row/column: 2.
Subblocks per clb: 1. Subblock LUT size: 4.
Fc value is fraction of tracks in a channel.
Fc_output: 1. Fc_input: 1. Fc_pad: 1.
Switch block type: Subset.
Distinct types of segments: 3.
Distinct types of user-specified switches: 3.
Reading the circuit netlist from
Successfully read
1826 blocks, 1791 nets, 0 global nets.
1750 clbs, 41 inputs, 35 outputs.
The circuit will be mapped into a 42 x 42 array of clbs.
Completed placement consistency check successfully.
Total moves attempted: 5131990.0
exit 0