| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| ; RUN: opt -S -O2 < %s | FileCheck %s |
| ; RUN: opt -S -passes='default<O2>' < %s | FileCheck %s |
| |
| ; FIXME: The br -> switch conversion blocks loop rotation. |
| |
| define i64 @test() { |
| ; CHECK-LABEL: @test( |
| ; CHECK-NEXT: start: |
| ; CHECK-NEXT: br label [[BB10:%.*]] |
| ; CHECK: bb10: |
| ; CHECK-NEXT: [[ITER1_SROA_5_0:%.*]] = phi i64 [ 100000, [[START:%.*]] ], [ [[SPEC_SELECT:%.*]], [[BB3_I_I:%.*]] ] |
| ; CHECK-NEXT: [[ITER1_SROA_9_0:%.*]] = phi i8 [ 2, [[START]] ], [ [[TMP3:%.*]], [[BB3_I_I]] ] |
| ; CHECK-NEXT: [[COUNT_1:%.*]] = phi i64 [ 0, [[START]] ], [ [[TMP4:%.*]], [[BB3_I_I]] ] |
| ; CHECK-NEXT: switch i8 [[ITER1_SROA_9_0]], label [[BB12:%.*]] [ |
| ; CHECK-NEXT: i8 2, label [[BB3_I_I]] |
| ; CHECK-NEXT: i8 0, label [[BB3_I_I]] |
| ; CHECK-NEXT: ] |
| ; CHECK: bb3.i.i: |
| ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[ITER1_SROA_5_0]], 0 |
| ; CHECK-NEXT: [[TMP3]] = zext i1 [[TMP2]] to i8 |
| ; CHECK-NEXT: [[SPEC_SELECT]] = tail call i64 @llvm.usub.sat.i64(i64 [[ITER1_SROA_5_0]], i64 1) |
| ; CHECK-NEXT: [[TMP4]] = add i64 [[COUNT_1]], [[ITER1_SROA_5_0]] |
| ; CHECK-NEXT: br label [[BB10]] |
| ; CHECK: bb12: |
| ; CHECK-NEXT: ret i64 [[COUNT_1]] |
| ; |
| start: |
| br label %bb10 |
| |
| bb10: ; preds = %bb3.i.i, %bb6 |
| %iter1.sroa.5.0 = phi i64 [ 100000, %start ], [ %spec.select, %bb3.i.i ] |
| %iter1.sroa.9.0 = phi i8 [ 2, %start ], [ %tmp3, %bb3.i.i ] |
| %count.1 = phi i64 [ 0, %start ], [ %tmp4, %bb3.i.i ] |
| %c1 = icmp eq i8 %iter1.sroa.9.0, 2 |
| %c2 = icmp eq i8 %iter1.sroa.9.0, 0 |
| %c3 = or i1 %c1, %c2 |
| br i1 %c3, label %bb3.i.i, label %bb12 |
| |
| bb3.i.i: ; preds = %bb10, %bb10 |
| %tmp2 = icmp eq i64 %iter1.sroa.5.0, 0 |
| %tmp3 = zext i1 %tmp2 to i8 |
| %_5.0.i.i.i.i = add i64 %iter1.sroa.5.0, -1 |
| %spec.select = select i1 %tmp2, i64 0, i64 %_5.0.i.i.i.i |
| |
| %tmp4 = add i64 %count.1, %iter1.sroa.5.0 |
| br label %bb10 |
| |
| bb12: ; preds = %bb10 |
| ret i64 %count.1 |
| } |
