llvm/test/CodeGen/X86/pr122580.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s

@g_180 = external global i8
@g_1032 = external global [2 x i32]

define i32 @PR122580(ptr %0) {
; CHECK-LABEL: PR122580:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movq g_180@GOTPCREL(%rip), %rax
; CHECK-NEXT:    cmpb $0, (%rax)
; CHECK-NEXT:    movl $1, %eax
; CHECK-NEXT:    movl $878456583, %ecx # imm = 0x345C2F07
; CHECK-NEXT:    cmovnel %eax, %ecx
; CHECK-NEXT:    movq g_1032@GOTPCREL(%rip), %rax
; CHECK-NEXT:    movl $0, (%rax)
; CHECK-NEXT:    movl %ecx, (%rdi)
; CHECK-NEXT:    xorl %eax, %eax
; CHECK-NEXT:    retq
entry:
  %.b577 = load i1, ptr @g_180, align 4
  %1 = select i1 %.b577, i32 1, i32 878456582
  store i32 0, ptr @g_1032, align 4
  %.b576 = load i1, ptr @g_180, align 4
  %2 = select i1 %.b576, i32 1, i32 878456582
  %or542.1.i = or i32 %2, %1
  store i32 0, ptr @g_1032, align 4
  %.b575 = load i1, ptr @g_180, align 4
  %3 = select i1 %.b575, i32 1, i32 878456582
  %or542.2.i = or i32 %3, %or542.1.i
  %or542.3.i = or i32 %or542.2.i, 1
  store i32 %or542.3.i, ptr %0, align 4
  %4 = load i32, ptr %0, align 4
  %div.i1796.i = sdiv i32 %4, 1096912269
  %5 = tail call i32 @llvm.ctpop.i32(i32 %div.i1796.i)
  ret i32 %5
}