llvm/test/CodeGen/AMDGPU/insert-handle-flat-vmem-ds.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=polaris10 -run-pass si-pre-emit-peephole -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=polaris10 -passes si-pre-emit-peephole %s -o - | FileCheck %s

---

name: skip_execz_flat
body: |
  ; CHECK-LABEL: name: skip_execz_flat
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x7fffffff)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   FLAT_STORE_DWORD undef $vgpr1_vgpr2, $vgpr0, 0, 0, implicit $exec, implicit $flat_scr
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1(0x70000000), %bb.2(0x00000001)
    S_CBRANCH_EXECZ   %bb.2, implicit $exec

  bb.1:
    successors: %bb.2
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    FLAT_STORE_DWORD undef $vgpr1_vgpr2, $vgpr0, 0, 0, implicit $exec, implicit $flat_scr

  bb.2:
    S_ENDPGM 0
...

---

name: skip_execz_mubuf
body: |
  ; CHECK-LABEL: name: skip_execz_mubuf
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x7fffffff)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, undef $sgpr4, 0, 0, 0, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1(0x70000000), %bb.2(0x00000001)
    S_CBRANCH_EXECZ  %bb.2, implicit $exec

  bb.1:
    successors: %bb.2
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, undef $sgpr4, 0, 0, 0, implicit $exec

  bb.2:
    S_ENDPGM 0
...

---

name: skip_execz_ds
body: |
  ; CHECK-LABEL: name: skip_execz_ds
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x7fffffff)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   DS_WRITE_B32 $vgpr0, $vgpr0, 0, 0, implicit $m0, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1(0x70000000), %bb.2(0x00000001)
    S_CBRANCH_EXECZ %bb.2, implicit $exec

  bb.1:
    successors: %bb.2
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    DS_WRITE_B32 $vgpr0, $vgpr0, 0, 0, implicit $m0, implicit $exec

  bb.2:
    S_ENDPGM 0
...