| { | 
 |    "context" : "{  :  }", | 
 |    "name" : "bb1 => bb15", | 
 |    "statements" : [ | 
 |       { | 
 |          "accesses" : [ | 
 |             { | 
 |                "kind" : "read", | 
 |                "relation" : "{ Stmt_bb2__TO__bb13[i0] -> MemRef_A[i0] }" | 
 |             }, | 
 |             { | 
 |                "kind" : "read", | 
 |                "relation" : "{ Stmt_bb2__TO__bb13[i0] -> MemRef_C[42] }" | 
 |             }, | 
 |             { | 
 |                "kind" : "write", | 
 |                "relation" : "{ Stmt_bb2__TO__bb13[i0] -> MemRef_C[42] }" | 
 |             }, | 
 |             { | 
 |                "kind" : "read", | 
 |                "relation" : "{ Stmt_bb2__TO__bb13[i0] -> MemRef_B[113] }" | 
 |             }, | 
 |             { | 
 |                "kind" : "write", | 
 |                "relation" : "{ Stmt_bb2__TO__bb13[i0] -> MemRef_B[113] }" | 
 |             } | 
 |          ], | 
 |          "domain" : "{ Stmt_bb2__TO__bb13[i0] : i0 <= 9 and i0 >= 0 }", | 
 |          "name" : "Stmt_bb2__TO__bb13", | 
 |          "schedule" : "{ Stmt_bb2__TO__bb13[i0] -> [i0] }" | 
 |       } | 
 |    ] | 
 | } |