llvm/test/CodeGen/RISCV/pr80052.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc %s -mtriple=riscv64 -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - | FileCheck %s

---
name:            foo
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    4
  localFrameSize:  4
stack:
  - { id: 0, size: 1, alignment: 4, local-offset: -4 }
machineFunctionInfo:
  varArgsFrameIndex: 0
  varArgsSaveSize: 0
body:             |
  bb.0.entry:
    ; To trick stack-slot-colouring to run its dead-store-elimination phase,
    ; which is at fault, we need the register allocator to run, and spill in two
    ; places that can have their slots merged. Achieve this by volatile-loading
    ; data into all allocatable GPRs except $x31. Then, volatile storing them
    ; later, leaving regalloc only $x31 to play with in the middle.
    $x1 = LW %stack.0, 0 :: (volatile load (s32))
    $x5 = LW %stack.0, 0 :: (volatile load (s32))
    $x6 = LW %stack.0, 0 :: (volatile load (s32))
    $x7 = LW %stack.0, 0 :: (volatile load (s32))
    $x8 = LW %stack.0, 0 :: (volatile load (s32))
    $x9 = LW %stack.0, 0 :: (volatile load (s32))
    $x10 = LW %stack.0, 0 :: (volatile load (s32))
    $x11 = LW %stack.0, 0 :: (volatile load (s32))
    $x12 = LW %stack.0, 0 :: (volatile load (s32))
    $x13 = LW %stack.0, 0 :: (volatile load (s32))
    $x14 = LW %stack.0, 0 :: (volatile load (s32))
    $x15 = LW %stack.0, 0 :: (volatile load (s32))
    $x16 = LW %stack.0, 0 :: (volatile load (s32))
    $x17 = LW %stack.0, 0 :: (volatile load (s32))
    $x18 = LW %stack.0, 0 :: (volatile load (s32))
    $x19 = LW %stack.0, 0 :: (volatile load (s32))
    $x20 = LW %stack.0, 0 :: (volatile load (s32))
    $x21 = LW %stack.0, 0 :: (volatile load (s32))
    $x22 = LW %stack.0, 0 :: (volatile load (s32))
    $x23 = LW %stack.0, 0 :: (volatile load (s32))
    $x24 = LW %stack.0, 0 :: (volatile load (s32))
    $x25 = LW %stack.0, 0 :: (volatile load (s32))
    $x26 = LW %stack.0, 0 :: (volatile load (s32))
    $x27 = LW %stack.0, 0 :: (volatile load (s32))
    $x28 = LW %stack.0, 0 :: (volatile load (s32))
    $x29 = LW %stack.0, 0 :: (volatile load (s32))
    $x30 = LW %stack.0, 0 :: (volatile load (s32))

    ; Force the first spill.
    %0:gpr = LW %stack.0, 0 :: (volatile load (s32))
    %1:gpr = LW %stack.0, 0 :: (volatile load (s32))
    SW %1, %stack.0, 0 :: (volatile store (s32))
    SW %0, %stack.0, 0 :: (volatile store (s32))

    ; CHECK: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))
    ; CHECK-NEXT: SD killed renamable $x31, %stack.1, 0 :: (store (s64) into %stack.1)
    ; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))
    ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))
    ; CHECK-NEXT: renamable $x31 = LD %stack.1, 0 :: (load (s64) from %stack.1)
    ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))

    ; stack-slot-coloring doesn't know that a write to $x0 is discarded.
    dead $x0 = LW %stack.0, 0 :: (volatile load (s32))
    ; This stores 0 rather than the result of the preceding load since $x0
    ; is special.
    ; We don't want this store to be deleted.
    SW $x0, %stack.0, 0 :: (volatile store (s32))

    ; CHECK-NEXT: dead $x0 = LW %stack.0, 0 :: (volatile load (s32))
    ; CHECK-NEXT: SW $x0, %stack.0, 0 :: (volatile store (s32))

    ; Force a second spill
    %2:gpr = LW %stack.0, 0 :: (volatile load (s32))
    %3:gpr = LW %stack.0, 0 :: (volatile load (s32))
    SW %3, %stack.0, 0 :: (volatile store (s32))
    SW %2, %stack.0, 0 :: (volatile store (s32))

    ; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))
    ; CHECK-NEXT: SD killed renamable $x31, %stack.1, 0 :: (store (s64) into %stack.1)
    ; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))
    ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))
    ; CHECK-NEXT: renamable $x31 = LD %stack.1, 0 :: (load (s64) from %stack.1)
    ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))

    SW $x1, %stack.0, 0 :: (volatile store (s32))
    SW $x5, %stack.0, 0 :: (volatile store (s32))
    SW $x6, %stack.0, 0 :: (volatile store (s32))
    SW $x7, %stack.0, 0 :: (volatile store (s32))
    SW $x8, %stack.0, 0 :: (volatile store (s32))
    SW $x9, %stack.0, 0 :: (volatile store (s32))
    SW $x10, %stack.0, 0 :: (volatile store (s32))
    SW $x11, %stack.0, 0 :: (volatile store (s32))
    SW $x12, %stack.0, 0 :: (volatile store (s32))
    SW $x13, %stack.0, 0 :: (volatile store (s32))
    SW $x14, %stack.0, 0 :: (volatile store (s32))
    SW $x15, %stack.0, 0 :: (volatile store (s32))
    SW $x16, %stack.0, 0 :: (volatile store (s32))
    SW $x17, %stack.0, 0 :: (volatile store (s32))
    SW $x18, %stack.0, 0 :: (volatile store (s32))
    SW $x19, %stack.0, 0 :: (volatile store (s32))
    SW $x20, %stack.0, 0 :: (volatile store (s32))
    SW $x21, %stack.0, 0 :: (volatile store (s32))
    SW $x22, %stack.0, 0 :: (volatile store (s32))
    SW $x23, %stack.0, 0 :: (volatile store (s32))
    SW $x24, %stack.0, 0 :: (volatile store (s32))
    SW $x25, %stack.0, 0 :: (volatile store (s32))
    SW $x26, %stack.0, 0 :: (volatile store (s32))
    SW $x27, %stack.0, 0 :: (volatile store (s32))
    SW $x28, %stack.0, 0 :: (volatile store (s32))
    SW $x29, %stack.0, 0 :: (volatile store (s32))
    SW $x30, %stack.0, 0 :: (volatile store (s32))
    PseudoRET

...