llvm/test/CodeGen/PowerPC/subreg-coalescer.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s \
# RUN:   -verify-coalescing --run-pass=register-coalescer -o - | FileCheck %s

# Check that the register coalescer correctly handles merging live ranges over
# SUBREG_TO_REG on PowerPC. The -verify-coalescing option will give an error if
# this is incorrect.

---
name: check_subregs
alignment:       16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x3

    ; CHECK-LABEL: name: check_subregs
    ; CHECK: liveins: $x3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
    ; CHECK-NEXT: [[LFSUX:%[0-9]+]]:f8rc, dead [[LFSUX1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LFSUX [[COPY]], [[COPY]]
    ; CHECK-NEXT: undef [[FRSP:%[0-9]+]].sub_64:vslrc = FRSP [[LFSUX]], implicit $rm
    ; CHECK-NEXT: [[XVCVDPSP:%[0-9]+]]:vrrc = XVCVDPSP [[FRSP]], implicit $rm
    ; CHECK-NEXT: $v2 = COPY [[XVCVDPSP]]
    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $v2
    %0:g8rc_and_g8rc_nox0 = COPY $x3
    %1:f8rc, %2:g8rc_and_g8rc_nox0 = LFSUX %0, %0
    %3:f4rc = FRSP killed %1, implicit $rm
    %4:vslrc = SUBREG_TO_REG 1, %3, %subreg.sub_64
    %5:vrrc = XVCVDPSP killed %4, implicit $rm
    $v2 = COPY %5
    BLR8 implicit $lr8, implicit $rm, implicit $v2
...