llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -run-pass=ppc-mi-peepholes \
# RUN: -simplify-mir %s -o - | FileCheck %s
---
name:            poc
alignment:       16
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: poc
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.1, %bb.2
  ; CHECK-NEXT:   liveins: $x3, $x4, $x5, $x6
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:g8rc = COPY killed $x6
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:g8rc = COPY killed $x5
  ; CHECK-NEXT:   dead %2:g8rc = COPY killed $x4
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
  ; CHECK-NEXT:   [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY1]], 1, implicit-def dead $cr0, implicit-def $cr0gt
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:crbitrc = COPY killed $cr0gt
  ; CHECK-NEXT:   BCn killed [[COPY3]], %bb.2
  ; CHECK-NEXT:   B %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   liveins: $x3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW killed $x3
  ; CHECK-NEXT:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR killed [[ANDI8_rec]], 2, 61
  ; CHECK-NEXT:   dead $x3 = COPY killed [[RLDICR]]
  ; CHECK-NEXT:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR killed [[EXTSW]], 2, 61
  ; CHECK-NEXT:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 killed [[COPY2]], killed [[RLDICR1]]
  ; CHECK-NEXT:   $x3 = COPY killed [[ADD8_]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit killed $x3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
  ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG killed [[DEF]], killed [[COPY4]], %subreg.sub_32
  ; CHECK-NEXT:   $x3 = COPY killed [[INSERT_SUBREG]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit killed $x3
  bb.0.entry:
    successors: %bb.1, %bb.2
    liveins: $x3, $x4, $x5, $x6

    %4:g8rc = COPY $x6
    %3:g8rc = COPY $x5
    %2:g8rc = COPY $x4
    %1:g8rc_and_g8rc_nox0 = COPY $x3
    %11:g8rc = ANDI8_rec %3, 1, implicit-def $cr0
    %6:crbitrc = COPY $cr0gt
    BCn killed %6, %bb.2
    B %bb.1

  bb.1:
    liveins: $x3

    %0:g8rc = EXTSW $x3
    %12:g8rc = RLDICR %11, 2, 61
    $x3 = COPY %12:g8rc
    %9:g8rc = RLDICR %0, 2, 61
    %10:g8rc = ADD8 %1, %9
    $x3 = COPY %10
    BLR8 implicit $lr8, implicit $rm, implicit $x3

  bb.2:
    %5:gprc = COPY %4.sub_32
    %8:g8rc = IMPLICIT_DEF
    %7:g8rc = INSERT_SUBREG %8, %5, %subreg.sub_32
    $x3 = COPY %7
    BLR8 implicit $lr8, implicit $rm, implicit $x3

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