llvm/test/CodeGen/PowerPC/cgp-select.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 -mcpu=pwr9 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s

define dso_local void @wibble(ptr nocapture readonly %arg, i32 signext %arg1, ptr nocapture %arg2, ptr nocapture %arg3) {
; CHECK-LABEL: wibble:
; CHECK:       # %bb.0: # %bb
; CHECK-NEXT:    lfs 0, 0(3)
; CHECK-NEXT:    li 7, 7
; CHECK-NEXT:    cmpwi 4, 2
; CHECK-NEXT:    xsaddsp 0, 0, 0
; CHECK-NEXT:    blt 0, .LBB0_5
; CHECK-NEXT:  # %bb.1: # %bb6
; CHECK-NEXT:    clrldi 4, 4, 32
; CHECK-NEXT:    addi 4, 4, -1
; CHECK-NEXT:    mtctr 4
; CHECK-NEXT:    li 4, 8
; CHECK-NEXT:    b .LBB0_3
; CHECK-NEXT:    .p2align 5
; CHECK-NEXT:  .LBB0_2: # %bb11
; CHECK-NEXT:    #
; CHECK-NEXT:    iselgt 7, 4, 7
; CHECK-NEXT:    addi 4, 4, 1
; CHECK-NEXT:    bdz .LBB0_5
; CHECK-NEXT:  .LBB0_3: # %bb11
; CHECK-NEXT:    #
; CHECK-NEXT:    lfsu 1, 4(3)
; CHECK-NEXT:    fcmpu 0, 1, 0
; CHECK-NEXT:    ble 0, .LBB0_2
; CHECK-NEXT:  # %bb.4:
; CHECK-NEXT:    xsaddsp 0, 1, 1
; CHECK-NEXT:    b .LBB0_2
; CHECK-NEXT:  .LBB0_5: # %bb8
; CHECK-NEXT:    stw 7, 0(5)
; CHECK-NEXT:    stfs 0, 0(6)
; CHECK-NEXT:    blr
bb:
  %tmp = load float, ptr %arg, align 4
  %tmp4 = fmul float %tmp, 2.000000e+00
  %tmp5 = icmp sgt i32 %arg1, 1
  br i1 %tmp5, label %bb6, label %bb8

bb6:                                              ; preds = %bb
  %tmp7 = zext i32 %arg1 to i64
  br label %bb11

bb8:                                              ; preds = %bb11, %bb
  %tmp9 = phi float [ %tmp4, %bb ], [ %tmp19, %bb11 ]
  %tmp10 = phi i32 [ 7, %bb ], [ %tmp22, %bb11 ]
  store i32 %tmp10, ptr %arg2, align 4
  store float %tmp9, ptr %arg3, align 4
  ret void

bb11:                                             ; preds = %bb11, %bb6
  %tmp12 = phi i64 [ 1, %bb6 ], [ %tmp23, %bb11 ]
  %tmp13 = phi i32 [ 7, %bb6 ], [ %tmp22, %bb11 ]
  %tmp14 = phi float [ %tmp4, %bb6 ], [ %tmp19, %bb11 ]
  %tmp15 = getelementptr inbounds float, ptr %arg, i64 %tmp12
  %tmp16 = load float, ptr %tmp15, align 4
  %tmp17 = fcmp ogt float %tmp16, %tmp14
  %tmp18 = fmul float %tmp16, 2.000000e+00
  %tmp19 = select i1 %tmp17, float %tmp18, float %tmp14
  %tmp20 = trunc i64 %tmp12 to i32
  %tmp21 = add i32 %tmp20, 7
  %tmp22 = select i1 %tmp17, i32 %tmp21, i32 %tmp13
  %tmp23 = add nuw nsw i64 %tmp12, 1
  %tmp24 = icmp eq i64 %tmp23, %tmp7
  br i1 %tmp24, label %bb8, label %bb11
}