llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s

;
; SMAX
;
define <vscale x 16 x i8> @smax_i8_pos(<vscale x 16 x i8> %a) {
; CHECK-LABEL: smax_i8_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smax z0.b, z0.b, #27
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 16 x i8> %a, splat(i8 27)
  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 27)
  ret <vscale x 16 x i8> %res
}

define <vscale x 16 x i8> @smax_i8_neg(<vscale x 16 x i8> %a) {
; CHECK-LABEL: smax_i8_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smax z0.b, z0.b, #-58
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 16 x i8> %a, splat(i8 -58)
  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 -58)
  ret <vscale x 16 x i8> %res
}

define <vscale x 8 x i16> @smax_i16_pos(<vscale x 8 x i16> %a) {
; CHECK-LABEL: smax_i16_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smax z0.h, z0.h, #27
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 8 x i16> %a, splat(i16 27)
  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 27)
  ret <vscale x 8 x i16> %res
}

define <vscale x 8 x i16> @smax_i16_neg(<vscale x 8 x i16> %a) {
; CHECK-LABEL: smax_i16_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smax z0.h, z0.h, #-58
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 8 x i16> %a, splat(i16 -58)
  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 -58)
  ret <vscale x 8 x i16> %res
}

define <vscale x 8 x i16> @smax_i16_out_of_range(<vscale x 8 x i16> %a) {
; CHECK-LABEL: smax_i16_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    dupm z1.b, #0x1
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    smax z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 8 x i16> %a, splat(i16 257)
  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 257)
  ret <vscale x 8 x i16> %res
}

define <vscale x 4 x i32> @smax_i32_pos(<vscale x 4 x i32> %a) {
; CHECK-LABEL: smax_i32_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smax z0.s, z0.s, #27
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 4 x i32> %a, splat(i32 27)
  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 27)
  ret <vscale x 4 x i32> %res
}

define <vscale x 4 x i32> @smax_i32_neg(<vscale x 4 x i32> %a) {
; CHECK-LABEL: smax_i32_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smax z0.s, z0.s, #-58
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 4 x i32> %a, splat(i32 -58)
  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 -58)
  ret <vscale x 4 x i32> %res
}

define <vscale x 4 x i32> @smax_i32_out_of_range(<vscale x 4 x i32> %a) {
; CHECK-LABEL: smax_i32_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z1.s, #-129 // =0xffffffffffffff7f
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    smax z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 4 x i32> %a, splat(i32 -129)
  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 -129)
  ret <vscale x 4 x i32> %res
}

define <vscale x 2 x i64> @smax_i64_pos(<vscale x 2 x i64> %a) {
; CHECK-LABEL: smax_i64_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smax z0.d, z0.d, #27
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 2 x i64> %a, splat(i64 27)
  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 27)
  ret <vscale x 2 x i64> %res
}

define <vscale x 2 x i64> @smax_i64_neg(<vscale x 2 x i64> %a) {
; CHECK-LABEL: smax_i64_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smax z0.d, z0.d, #-58
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 2 x i64> %a, splat(i64 -58)
  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 -58)
  ret <vscale x 2 x i64> %res
}

define <vscale x 2 x i64> @smax_i64_out_of_range(<vscale x 2 x i64> %a) {
; CHECK-LABEL: smax_i64_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z1.d, #65535 // =0xffff
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    smax z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 2 x i64> %a, splat(i64 65535)
  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 65535)
  ret <vscale x 2 x i64> %res
}

;
; SMIN
;
define <vscale x 16 x i8> @smin_i8_pos(<vscale x 16 x i8> %a) {
; CHECK-LABEL: smin_i8_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smin z0.b, z0.b, #27
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 16 x i8> %a, splat(i8 27)
  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 27)
  ret <vscale x 16 x i8> %res
}

define <vscale x 16 x i8> @smin_i8_neg(<vscale x 16 x i8> %a) {
; CHECK-LABEL: smin_i8_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smin z0.b, z0.b, #-58
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 16 x i8> %a, splat(i8 -58)
  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 -58)
  ret <vscale x 16 x i8> %res
}

define <vscale x 8 x i16> @smin_i16_pos(<vscale x 8 x i16> %a) {
; CHECK-LABEL: smin_i16_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smin z0.h, z0.h, #27
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 8 x i16> %a, splat(i16 27)
  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 27)
  ret <vscale x 8 x i16> %res
}

define <vscale x 8 x i16> @smin_i16_neg(<vscale x 8 x i16> %a) {
; CHECK-LABEL: smin_i16_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smin z0.h, z0.h, #-58
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 8 x i16> %a, splat(i16 -58)
  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 -58)
  ret <vscale x 8 x i16> %res
}

define <vscale x 8 x i16> @smin_i16_out_of_range(<vscale x 8 x i16> %a) {
; CHECK-LABEL: smin_i16_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    dupm z1.b, #0x1
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    smin z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 8 x i16> %a, splat(i16 257)
  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 257)
  ret <vscale x 8 x i16> %res
}

define <vscale x 4 x i32> @smin_i32_pos(<vscale x 4 x i32> %a) {
; CHECK-LABEL: smin_i32_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smin z0.s, z0.s, #27
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 4 x i32> %a, splat(i32 27)
  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 27)
  ret <vscale x 4 x i32> %res
}

define <vscale x 4 x i32> @smin_i32_neg(<vscale x 4 x i32> %a) {
; CHECK-LABEL: smin_i32_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smin z0.s, z0.s, #-58
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 4 x i32> %a, splat(i32 -58)
  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 -58)
  ret <vscale x 4 x i32> %res
}

define <vscale x 4 x i32> @smin_i32_out_of_range(<vscale x 4 x i32> %a) {
; CHECK-LABEL: smin_i32_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z1.s, #-129 // =0xffffffffffffff7f
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    smin z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 4 x i32> %a, splat(i32 -129)
  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 -129)
  ret <vscale x 4 x i32> %res
}

define <vscale x 2 x i64> @smin_i64_pos(<vscale x 2 x i64> %a) {
; CHECK-LABEL: smin_i64_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smin z0.d, z0.d, #27
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 2 x i64> %a, splat(i64 27)
  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 27)
  ret <vscale x 2 x i64> %res
}

define <vscale x 2 x i64> @smin_i64_neg(<vscale x 2 x i64> %a) {
; CHECK-LABEL: smin_i64_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smin z0.d, z0.d, #-58
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 2 x i64> %a, splat(i64 -58)
  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 -58)
  ret <vscale x 2 x i64> %res
}

define <vscale x 2 x i64> @smin_i64_out_of_range(<vscale x 2 x i64> %a) {
; CHECK-LABEL: smin_i64_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z1.d, #65535 // =0xffff
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    smin z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 2 x i64> %a, splat(i64 65535)
  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 65535)
  ret <vscale x 2 x i64> %res
}

;
; UMAX
;
define <vscale x 16 x i8> @umax_i8_pos(<vscale x 16 x i8> %a) {
; CHECK-LABEL: umax_i8_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umax z0.b, z0.b, #27
; CHECK-NEXT:    ret
  %cmp = icmp ugt <vscale x 16 x i8> %a, splat(i8 27)
  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 27)
  ret <vscale x 16 x i8> %res
}

define <vscale x 16 x i8> @umax_i8_large(<vscale x 16 x i8> %a) {
; CHECK-LABEL: umax_i8_large:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umax z0.b, z0.b, #129
; CHECK-NEXT:    ret
  %cmp = icmp ugt <vscale x 16 x i8> %a, splat(i8 129)
  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 129)
  ret <vscale x 16 x i8> %res
}

define <vscale x 8 x i16> @umax_i16_pos(<vscale x 8 x i16> %a) {
; CHECK-LABEL: umax_i16_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umax z0.h, z0.h, #27
; CHECK-NEXT:    ret
  %cmp = icmp ugt <vscale x 8 x i16> %a, splat(i16 27)
  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 27)
  ret <vscale x 8 x i16> %res
}

define <vscale x 8 x i16> @umax_i16_out_of_range(<vscale x 8 x i16> %a) {
; CHECK-LABEL: umax_i16_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    dupm z1.b, #0x1
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    umax z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT:    ret
  %cmp = icmp ugt <vscale x 8 x i16> %a, splat(i16 257)
  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 257)
  ret <vscale x 8 x i16> %res
}

define <vscale x 4 x i32> @umax_i32_pos(<vscale x 4 x i32> %a) {
; CHECK-LABEL: umax_i32_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umax z0.s, z0.s, #27
; CHECK-NEXT:    ret
  %cmp = icmp ugt <vscale x 4 x i32> %a, splat(i32 27)
  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 27)
  ret <vscale x 4 x i32> %res
}

define <vscale x 4 x i32> @umax_i32_out_of_range(<vscale x 4 x i32> %a) {
; CHECK-LABEL: umax_i32_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w8, #257 // =0x101
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    mov z1.s, w8
; CHECK-NEXT:    umax z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT:    ret
  %cmp = icmp ugt <vscale x 4 x i32> %a, splat(i32 257)
  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 257)
  ret <vscale x 4 x i32> %res
}

define <vscale x 2 x i64> @umax_i64_pos(<vscale x 2 x i64> %a) {
; CHECK-LABEL: umax_i64_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umax z0.d, z0.d, #27
; CHECK-NEXT:    ret
  %cmp = icmp ugt <vscale x 2 x i64> %a, splat(i64 27)
  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 27)
  ret <vscale x 2 x i64> %res
}

define <vscale x 2 x i64> @umax_i64_out_of_range(<vscale x 2 x i64> %a) {
; CHECK-LABEL: umax_i64_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z1.d, #65535 // =0xffff
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    umax z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT:    ret
  %cmp = icmp ugt <vscale x 2 x i64> %a, splat(i64 65535)
  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 65535)
  ret <vscale x 2 x i64> %res
}

;
; UMIN
;
define <vscale x 16 x i8> @umin_i8_pos(<vscale x 16 x i8> %a) {
; CHECK-LABEL: umin_i8_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umin z0.b, z0.b, #27
; CHECK-NEXT:    ret
  %cmp = icmp ult <vscale x 16 x i8> %a, splat(i8 27)
  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 27)
  ret <vscale x 16 x i8> %res
}

define <vscale x 16 x i8> @umin_i8_large(<vscale x 16 x i8> %a) {
; CHECK-LABEL: umin_i8_large:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umin z0.b, z0.b, #129
; CHECK-NEXT:    ret
  %cmp = icmp ult <vscale x 16 x i8> %a, splat(i8 129)
  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 129)
  ret <vscale x 16 x i8> %res
}

define <vscale x 8 x i16> @umin_i16_pos(<vscale x 8 x i16> %a) {
; CHECK-LABEL: umin_i16_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umin z0.h, z0.h, #27
; CHECK-NEXT:    ret
  %cmp = icmp ult <vscale x 8 x i16> %a, splat(i16 27)
  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 27)
  ret <vscale x 8 x i16> %res
}

define <vscale x 8 x i16> @umin_i16_out_of_range(<vscale x 8 x i16> %a) {
; CHECK-LABEL: umin_i16_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    dupm z1.b, #0x1
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    umin z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT:    ret
  %cmp = icmp ult <vscale x 8 x i16> %a, splat(i16 257)
  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 257)
  ret <vscale x 8 x i16> %res
}

define <vscale x 4 x i32> @umin_i32_pos(<vscale x 4 x i32> %a) {
; CHECK-LABEL: umin_i32_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umin z0.s, z0.s, #27
; CHECK-NEXT:    ret
  %cmp = icmp ult <vscale x 4 x i32> %a, splat(i32 27)
  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 27)
  ret <vscale x 4 x i32> %res
}

define <vscale x 4 x i32> @umin_i32_out_of_range(<vscale x 4 x i32> %a) {
; CHECK-LABEL: umin_i32_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w8, #257 // =0x101
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    mov z1.s, w8
; CHECK-NEXT:    umin z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT:    ret
  %cmp = icmp ult <vscale x 4 x i32> %a, splat(i32 257)
  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 257)
  ret <vscale x 4 x i32> %res
}

define <vscale x 2 x i64> @umin_i64_pos(<vscale x 2 x i64> %a) {
; CHECK-LABEL: umin_i64_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umin z0.d, z0.d, #27
; CHECK-NEXT:    ret
  %cmp = icmp ult <vscale x 2 x i64> %a, splat(i64 27)
  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 27)
  ret <vscale x 2 x i64> %res
}

define <vscale x 2 x i64> @umin_i64_out_of_range(<vscale x 2 x i64> %a) {
; CHECK-LABEL: umin_i64_out_of_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z1.d, #65535 // =0xffff
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    umin z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT:    ret
  %cmp = icmp ult <vscale x 2 x i64> %a, splat(i64 65535)
  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 65535)
  ret <vscale x 2 x i64> %res
}

;
; MUL
;
define <vscale x 16 x i8> @mul_i8_neg(<vscale x 16 x i8> %a) {
; CHECK-LABEL: mul_i8_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mul z0.b, z0.b, #-17
; CHECK-NEXT:    ret
  %res = mul <vscale x 16 x i8> %a, splat(i8 -17)
  ret <vscale x 16 x i8> %res
}

define <vscale x 16 x i8> @mul_i8_pos(<vscale x 16 x i8> %a) {
; CHECK-LABEL: mul_i8_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mul z0.b, z0.b, #105
; CHECK-NEXT:    ret
  %res = mul <vscale x 16 x i8> %a, splat(i8 105)
  ret <vscale x 16 x i8> %res
}

define <vscale x 8 x i16> @mul_i16_neg(<vscale x 8 x i16> %a) {
; CHECK-LABEL: mul_i16_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mul z0.h, z0.h, #-17
; CHECK-NEXT:    ret
  %res = mul <vscale x 8 x i16> %a, splat(i16 -17)
  ret <vscale x 8 x i16> %res
}

define <vscale x 8 x i16> @mul_i16_pos(<vscale x 8 x i16> %a) {
; CHECK-LABEL: mul_i16_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mul z0.h, z0.h, #105
; CHECK-NEXT:    ret
  %res = mul <vscale x 8 x i16> %a, splat(i16 105)
  ret <vscale x 8 x i16> %res
}

define <vscale x 4 x i32> @mul_i32_neg(<vscale x 4 x i32> %a) {
; CHECK-LABEL: mul_i32_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mul z0.s, z0.s, #-17
; CHECK-NEXT:    ret
  %res = mul <vscale x 4 x i32> %a, splat(i32 -17)
  ret <vscale x 4 x i32> %res
}

define <vscale x 4 x i32> @mul_i32_pos(<vscale x 4 x i32> %a) {
; CHECK-LABEL: mul_i32_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mul z0.s, z0.s, #105
; CHECK-NEXT:    ret
  %res = mul <vscale x 4 x i32> %a, splat(i32 105)
  ret <vscale x 4 x i32> %res
}

define <vscale x 2 x i64> @mul_i64_neg(<vscale x 2 x i64> %a) {
; CHECK-LABEL: mul_i64_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mul z0.d, z0.d, #-17
; CHECK-NEXT:    ret
  %res = mul <vscale x 2 x i64> %a, splat(i64 -17)
  ret <vscale x 2 x i64> %res
}

define <vscale x 2 x i64> @mul_i64_pos(<vscale x 2 x i64> %a) {
; CHECK-LABEL: mul_i64_pos:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mul z0.d, z0.d, #105
; CHECK-NEXT:    ret
  %res = mul <vscale x 2 x i64> %a, splat(i64 105)
  ret <vscale x 2 x i64> %res
}

define <vscale x 8 x i16> @mul_i16_range(<vscale x 8 x i16> %a) {
; CHECK-LABEL: mul_i16_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z1.h, #255 // =0xff
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT:    ret
  %res = mul <vscale x 8 x i16> %a, splat(i16 255)
  ret <vscale x 8 x i16> %res
}

define <vscale x 4 x i32> @mul_i32_range(<vscale x 4 x i32> %a) {
; CHECK-LABEL: mul_i32_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z1.s, #255 // =0xff
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT:    ret
  %res = mul <vscale x 4 x i32> %a, splat(i32 255)
  ret <vscale x 4 x i32> %res
}

define <vscale x 2 x i64> @mul_i64_range(<vscale x 2 x i64> %a) {
; CHECK-LABEL: mul_i64_range:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z1.d, #255 // =0xff
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT:    ret
  %res = mul <vscale x 2 x i64> %a, splat(i64 255)
  ret <vscale x 2 x i64> %res
}

; ASR

define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i8> %a){
; CHECK-LABEL: asr_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    asr z0.b, z0.b, #7
; CHECK-NEXT:    ret
  %lshr = ashr <vscale x 16 x i8> %a, splat(i8 7)
  ret <vscale x 16 x i8> %lshr
}

define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i16> %a){
; CHECK-LABEL: asr_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    asr z0.h, z0.h, #15
; CHECK-NEXT:    ret
  %ashr = ashr <vscale x 8 x i16> %a, splat(i16 15)
  ret <vscale x 8 x i16> %ashr
}

define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i32> %a){
; CHECK-LABEL: asr_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    asr z0.s, z0.s, #31
; CHECK-NEXT:    ret
  %ashr = ashr <vscale x 4 x i32> %a, splat(i32 31)
  ret <vscale x 4 x i32> %ashr
}

define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a){
; CHECK-LABEL: asr_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    asr z0.d, z0.d, #63
; CHECK-NEXT:    ret
  %ashr = ashr <vscale x 2 x i64> %a, splat(i64 63)
  ret <vscale x 2 x i64> %ashr
}

; LSL

define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i8> %a){
; CHECK-LABEL: lsl_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    lsl z0.b, z0.b, #7
; CHECK-NEXT:    ret
  %shl = shl <vscale x 16 x i8> %a, splat(i8 7)
  ret <vscale x 16 x i8> %shl
}

define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i16> %a){
; CHECK-LABEL: lsl_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    lsl z0.h, z0.h, #15
; CHECK-NEXT:    ret
  %shl = shl <vscale x 8 x i16> %a, splat(i16 15)
  ret <vscale x 8 x i16> %shl
}

define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i32> %a){
; CHECK-LABEL: lsl_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    lsl z0.s, z0.s, #31
; CHECK-NEXT:    ret
  %shl = shl <vscale x 4 x i32> %a, splat(i32 31)
  ret <vscale x 4 x i32> %shl
}

define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i64> %a){
; CHECK-LABEL: lsl_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    lsl z0.d, z0.d, #63
; CHECK-NEXT:    ret
  %shl = shl <vscale x 2 x i64> %a, splat(i64 63)
  ret <vscale x 2 x i64> %shl
}

; LSR

define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i8> %a){
; CHECK-LABEL: lsr_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    lsr z0.b, z0.b, #7
; CHECK-NEXT:    ret
  %lshr = lshr <vscale x 16 x i8> %a, splat(i8 7)
  ret <vscale x 16 x i8> %lshr
}

define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i16> %a){
; CHECK-LABEL: lsr_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    lsr z0.h, z0.h, #15
; CHECK-NEXT:    ret
  %lshr = lshr <vscale x 8 x i16> %a, splat(i16 15)
  ret <vscale x 8 x i16> %lshr
}

define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i32> %a){
; CHECK-LABEL: lsr_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    lsr z0.s, z0.s, #31
; CHECK-NEXT:    ret
  %lshr = lshr <vscale x 4 x i32> %a, splat(i32 31)
  ret <vscale x 4 x i32> %lshr
}

define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a){
; CHECK-LABEL: lsr_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    lsr z0.d, z0.d, #63
; CHECK-NEXT:    ret
  %lshr = lshr <vscale x 2 x i64> %a, splat(i64 63)
  ret <vscale x 2 x i64> %lshr
}

define <vscale x 4 x i32> @sdiv_const(<vscale x 4 x i32> %a) #0 {
; CHECK-LABEL: sdiv_const:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    mov z1.s, #3 // =0x3
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    sdiv z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT:    ret
entry:
  %div = sdiv <vscale x 4 x i32> %a, splat (i32 3)
  ret <vscale x 4 x i32> %div
}

define <vscale x 4 x i32> @udiv_const(<vscale x 4 x i32> %a) #0 {
; CHECK-LABEL: udiv_const:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    mov z1.s, #3 // =0x3
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    udiv z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT:    ret
entry:
  %div = udiv <vscale x 4 x i32> %a, splat (i32 3)
  ret <vscale x 4 x i32> %div
}

;
; UQSUB
;
define <vscale x 8 x i16> @uqsub(<vscale x 8 x i16> %a) {
; CHECK-LABEL: uqsub:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uqsub z0.h, z0.h, #32768 // =0x8000
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 8 x i16> %a, zeroinitializer
  %sub = xor <vscale x 8 x i16> %a, splat (i16 -32768)
  %sel = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %sub, <vscale x 8 x i16> zeroinitializer
  ret <vscale x 8 x i16> %sel
}

attributes #0 = { minsize }