| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 |
| # RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=none %s -o - | FileCheck %s |
| |
| # During the MachineVerifier, it assumes that used registers have been defined |
| # In this test case, while $v12_v13_v14_v15_v16 covers $v14_v15, |
| # $v14_v15 is not a sub-register of $v14m2 even though they share the same register. |
| # This corner case can be resolved by checking the register using RegUnit. |
| |
| ... |
| --- |
| name: func |
| tracksRegLiveness: true |
| tracksDebugUserValues: true |
| body: | |
| bb.0: |
| liveins: $v0, $v8, $v9, $v10, $v11 |
| |
| ; CHECK-LABEL: name: func |
| ; CHECK: liveins: $v0, $v8, $v9, $v10, $v11 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16, implicit $vtype |
| renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype |
| $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16, implicit $vtype |
| |
| ... |
