llvm/test/CodeGen/X86/pr116153.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s

define void @_test_func(<16 x half> %0) #0 {
; CHECK-LABEL: _test_func:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm0[3,3,3,3,4,5,6,7]
; CHECK-NEXT:    vcvtph2ps %xmm1, %xmm1
; CHECK-NEXT:    xorl %eax, %eax
; CHECK-NEXT:    vucomiss %xmm1, %xmm1
; CHECK-NEXT:    movl $65535, %ecx # imm = 0xFFFF
; CHECK-NEXT:    movl $0, %edx
; CHECK-NEXT:    cmovnpl %ecx, %edx
; CHECK-NEXT:    vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-NEXT:    vcvtph2ps %xmm1, %xmm1
; CHECK-NEXT:    vucomiss %xmm1, %xmm1
; CHECK-NEXT:    movl $0, %esi
; CHECK-NEXT:    cmovnpl %ecx, %esi
; CHECK-NEXT:    vpshuflw {{.*#+}} xmm1 = xmm0[1,1,1,1,4,5,6,7]
; CHECK-NEXT:    vcvtph2ps %xmm1, %xmm1
; CHECK-NEXT:    vucomiss %xmm1, %xmm1
; CHECK-NEXT:    movl $0, %edi
; CHECK-NEXT:    cmovnpl %ecx, %edi
; CHECK-NEXT:    vcvtph2ps %xmm0, %xmm0
; CHECK-NEXT:    vucomiss %xmm0, %xmm0
; CHECK-NEXT:    cmovnpl %ecx, %eax
; CHECK-NEXT:    vmovd %eax, %xmm0
; CHECK-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0
; CHECK-NEXT:    vpinsrw $2, %esi, %xmm0, %xmm0
; CHECK-NEXT:    vpinsrw $3, %edx, %xmm0, %xmm0
; CHECK-NEXT:    vpunpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; CHECK-NEXT:    vxorps %xmm1, %xmm1, %xmm1
; CHECK-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vmovdqu %xmm1, 16
; CHECK-NEXT:    vmovdqu %xmm0, 0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %2 = fcmp ord <16 x half> %0, zeroinitializer
  %3 = sext <16 x i1> %2 to <16 x i32>
  %4 = shufflevector <16 x i32> %3, <16 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %5 = tail call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %4, <4 x i32> zeroinitializer)
  %6 = shufflevector <8 x i16> %5, <8 x i16> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %7 = bitcast <16 x i16> %6 to <32 x i8>
  store <32 x i8> %7, ptr null, align 1
  ret void
}

declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>)

attributes #0 = { "target-features"="+aes,+avx,+avx2,+avx512f,+avx512vnni,+cmov,+crc32,+cx16,+cx8,+evex512,+f16c,+fma,+fxsr,+mmx,+pclmul,+popcnt,+prfchw,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" }