llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le -mcpu=pwr9 < %s | FileCheck %s

; Widen to <16 x i8>
define <12 x i8> @zext_abdu(<12 x i8> %a, <12 x i8> %b) {
; CHECK-LABEL: zext_abdu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vabsdub 2, 2, 3
; CHECK-NEXT:    blr
entry:
  %aa = zext <12 x i8> %a to <12 x i32>
  %bb = zext <12 x i8> %b to <12 x i32>
  %s = sub nsw <12 x i32> %aa, %bb
  %c = icmp slt <12 x i32> %s, zeroinitializer
  %ss = sub nsw <12 x i32> zeroinitializer, %s
  %sel = select <12 x i1> %c, <12 x i32> %ss, <12 x i32> %s
  %ret = trunc <12 x i32> %sel to <12 x i8>
  ret <12 x i8> %ret
}