llvm/test/CodeGen/PowerPC/inline-asm-physical-fpr-spe.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
; RUN:          -mattr=+spe |  FileCheck %s

define i32 @test_f32(float %x) {
; CHECK-LABEL: test_f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    stwu 1, -16(1)
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    .cfi_offset r31, -4
; CHECK-NEXT:    stw 3, 8(1)
; CHECK-NEXT:    stw 31, 12(1) # 4-byte Folded Spill
; CHECK-NEXT:    lwz 3, 8(1)
; CHECK-NEXT:    #APP
; CHECK-NEXT:    efsctsi 31, 3
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    mr 3, 31
; CHECK-NEXT:    lwz 31, 12(1) # 4-byte Folded Reload
; CHECK-NEXT:    addi 1, 1, 16
; CHECK-NEXT:    blr
entry:
  %0 = call i32 asm sideeffect "efsctsi $0, $1", "={f31},f"(float %x)
  ret i32 %0
}

define i32 @test_f64(double %x) {
; CHECK-LABEL: test_f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    evmergelo 3, 3, 4
; CHECK-NEXT:    #APP
; CHECK-NEXT:    efdctsi 0, 3
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    mr 3, 0
; CHECK-NEXT:    blr
entry:
  %0 = call i32 asm sideeffect "efdctsi $0, $1", "={f0},d"(double %x)
  ret i32 %0
}