| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| |
| ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s |
| |
| define <3 x half> @bitcast_v3bf16_to_v3f16(<3 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3bf16_to_v3f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v0 |
| ; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB0_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB0_4 |
| ; GCN-NEXT: .LBB0_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB0_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB0_2 |
| ; GCN-NEXT: .LBB0_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v5 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v3 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3bf16_to_v3f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB0_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 |
| ; VI-NEXT: s_movk_i32 s6, 0x7fff |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc |
| ; VI-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 |
| ; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v2, 16 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x7fc00000 |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: .LBB0_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3bf16_to_v3f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB0_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add3_u32 v3, v3, v2, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc |
| ; GFX9-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v3, v3, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc |
| ; GFX9-NEXT: s_mov_b32 s6, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v0, v0, v2, s6 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fc0 |
| ; GFX9-NEXT: v_alignbit_b32 v1, s6, v1, 16 |
| ; GFX9-NEXT: .LBB0_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v3bf16_to_v3f16: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB0_2 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2 |
| ; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1 |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2 |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff |
| ; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v3, v7 :: v_dual_mov_b32 v3, 0x7fc0 |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h |
| ; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v5 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0 |
| ; GFX11-TRUE16-NEXT: .LBB0_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v3bf16_to_v3f16: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v2 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB0_2 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1 |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2 |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302 |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, 0x7fc0, v1, 16 |
| ; GFX11-FAKE16-NEXT: .LBB0_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <3 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <3 x bfloat> %a1 to <3 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x bfloat> %a to <3 x half> |
| br label %end |
| |
| end: |
| %phi = phi <3 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x half> %phi |
| } |
| |
| define <3 x bfloat> @bitcast_v3f16_to_v3bf16(<3 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3f16_to_v3bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB1_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB1_4 |
| ; GCN-NEXT: .LBB1_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB1_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB1_2 |
| ; GCN-NEXT: .LBB1_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v3 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3f16_to_v3bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v3, 0x200 |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 |
| ; VI-NEXT: v_add_f16_e32 v2, 0x200, v0 |
| ; VI-NEXT: v_add_f16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v2, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, 0x7e000000, v1 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3f16_to_v3bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3f16_to_v3bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v2 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <3 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <3 x half> %a1 to <3 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x half> %a to <3 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <3 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x bfloat> %phi |
| } |
| |
| define <3 x i16> @bitcast_v3bf16_to_v3i16(<3 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3bf16_to_v3i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v0 |
| ; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB2_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB2_4 |
| ; GCN-NEXT: .LBB2_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB2_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB2_2 |
| ; GCN-NEXT: .LBB2_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v5 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v1 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_alignbit_b32 v0, v3, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3bf16_to_v3i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB2_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 |
| ; VI-NEXT: s_movk_i32 s6, 0x7fff |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc |
| ; VI-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 |
| ; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v2, 16 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x7fc00000 |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: .LBB2_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3bf16_to_v3i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB2_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add3_u32 v3, v3, v2, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc |
| ; GFX9-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v3, v3, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc |
| ; GFX9-NEXT: s_mov_b32 s6, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v0, v0, v2, s6 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fc0 |
| ; GFX9-NEXT: v_alignbit_b32 v1, s6, v1, 16 |
| ; GFX9-NEXT: .LBB2_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v3bf16_to_v3i16: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB2_2 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2 |
| ; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1 |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2 |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0 |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2 |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, 0x7fc0, 16, v1 |
| ; GFX11-TRUE16-NEXT: .LBB2_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v3bf16_to_v3i16: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v2 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB2_2 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1 |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2 |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v0, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302 |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, 0x7fc0, v1, 16 |
| ; GFX11-FAKE16-NEXT: .LBB2_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <3 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <3 x bfloat> %a1 to <3 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x bfloat> %a to <3 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <3 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x i16> %phi |
| } |
| |
| define <3 x bfloat> @bitcast_v3i16_to_v3bf16(<3 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3i16_to_v3bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v4, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB3_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB3_4 |
| ; GCN-NEXT: .LBB3_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB3_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v4 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB3_2 |
| ; GCN-NEXT: .LBB3_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v4 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3i16_to_v3bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v2, 3 |
| ; VI-NEXT: v_add_u16_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v0 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3i16_to_v3bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3i16_to_v3bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v2 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <3 x i16> %a, splat (i16 3) |
| %a2 = bitcast <3 x i16> %a1 to <3 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x i16> %a to <3 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <3 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x bfloat> %phi |
| } |
| |
| define <3 x i16> @bitcast_v3f16_to_v3i16(<3 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3f16_to_v3i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB4_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 |
| ; GCN-NEXT: .LBB4_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3f16_to_v3i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v3, 0x200 |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 |
| ; VI-NEXT: v_add_f16_e32 v2, 0x200, v0 |
| ; VI-NEXT: v_add_f16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v2, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, 0x7e000000, v1 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3f16_to_v3i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3f16_to_v3i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v2 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <3 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <3 x half> %a1 to <3 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x half> %a to <3 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <3 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x i16> %phi |
| } |
| |
| define <3 x half> @bitcast_v3i16_to_v3f16(<3 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v3i16_to_v3f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v6, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v5, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB5_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB5_4 |
| ; GCN-NEXT: .LBB5_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB5_3: ; %cmp.false |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v6 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB5_2 |
| ; GCN-NEXT: .LBB5_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v3i16_to_v3f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v2, 3 |
| ; VI-NEXT: v_add_u16_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v0 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v3i16_to_v3f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v3i16_to_v3f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v2 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <3 x i16> %a, splat (i16 3) |
| %a2 = bitcast <3 x i16> %a1 to <3 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <3 x i16> %a to <3 x half> |
| br label %end |
| |
| end: |
| %phi = phi <3 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <3 x half> %phi |
| } |
