| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| |
| ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s |
| |
| define <5 x float> @bitcast_v5i32_to_v5f32(<5 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v5i32_to_v5f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB0_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v3 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v1 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: .LBB0_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v5i32_to_v5f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v5i32_to_v5f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v4, 3, v4 |
| ; GFX9-NEXT: v_add_u32_e32 v3, 3, v3 |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v5i32_to_v5f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <5 x i32> %a, splat (i32 3) |
| %a2 = bitcast <5 x i32> %a1 to <5 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <5 x i32> %a to <5 x float> |
| br label %end |
| |
| end: |
| %phi = phi <5 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <5 x float> %phi |
| } |
| |
| define <5 x i32> @bitcast_v5f32_to_v5i32(<5 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v5f32_to_v5i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB1_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GCN-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: .LBB1_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v5f32_to_v5i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; VI-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v5f32_to_v5i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v5f32_to_v5i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3 |
| ; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1 |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <5 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <5 x float> %a1 to <5 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <5 x float> %a to <5 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <5 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <5 x i32> %phi |
| } |
| |
| define <10 x i16> @bitcast_v5i32_to_v10i16(<5 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v5i32_to_v10i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v8, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v2, v1 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB2_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB2_4 |
| ; GCN-NEXT: .LBB2_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB2_3: ; %cmp.false |
| ; GCN-NEXT: v_alignbit_b32 v9, s4, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB2_2 |
| ; GCN-NEXT: .LBB2_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, s4, v8, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v5i32_to_v10i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v5i32_to_v10i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v4, 3, v4 |
| ; GFX9-NEXT: v_add_u32_e32 v3, 3, v3 |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v5i32_to_v10i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <5 x i32> %a, splat (i32 3) |
| %a2 = bitcast <5 x i32> %a1 to <10 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <5 x i32> %a to <10 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <10 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <10 x i16> %phi |
| } |
| |
| define <5 x i32> @bitcast_v10i16_to_v5i32(<10 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v10i16_to_v5i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v13, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v12, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v11, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB3_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB3_4 |
| ; GCN-NEXT: .LBB3_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB3_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v11 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v12 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v13 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v8 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v10 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v14 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v5 |
| ; GCN-NEXT: v_or_b32_e32 v3, v3, v7 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v9 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB3_2 |
| ; GCN-NEXT: .LBB3_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v11 |
| ; GCN-NEXT: s_mov_b32 s6, 0x30000 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v12 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v13 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_or_b32_e32 v0, v10, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v14, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v5, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v7, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v9, v4 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v10i16_to_v5i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB3_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v6, 3 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v4 |
| ; VI-NEXT: v_add_u16_sdwa v4, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v4, v5, v4 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v3 |
| ; VI-NEXT: v_add_u16_sdwa v3, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v3, v5, v3 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v2 |
| ; VI-NEXT: v_add_u16_sdwa v2, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v5, v2 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v1 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v5, v1 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v5, v0 |
| ; VI-NEXT: .LBB3_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v10i16_to_v5i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v10i16_to_v5i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <10 x i16> %a, splat (i16 3) |
| %a2 = bitcast <10 x i16> %a1 to <5 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <10 x i16> %a to <5 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <5 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <5 x i32> %phi |
| } |
| |
| define <10 x half> @bitcast_v5i32_to_v10f16(<5 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v5i32_to_v10f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v14, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v13, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v12, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v11, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v10, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB4_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB4_4 |
| ; GCN-NEXT: .LBB4_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB4_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v14 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v13 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v12 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v11 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v12 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v16 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v10 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB4_2 |
| ; GCN-NEXT: .LBB4_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v10 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v11 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v12 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v13 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v5i32_to_v10f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v5i32_to_v10f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v4, 3, v4 |
| ; GFX9-NEXT: v_add_u32_e32 v3, 3, v3 |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v5i32_to_v10f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <5 x i32> %a, splat (i32 3) |
| %a2 = bitcast <5 x i32> %a1 to <10 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <5 x i32> %a to <10 x half> |
| br label %end |
| |
| end: |
| %phi = phi <10 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <10 x half> %phi |
| } |
| |
| define <5 x i32> @bitcast_v10f16_to_v5i32(<10 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v10f16_to_v5i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v11, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v8 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB5_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB5_4 |
| ; GCN-NEXT: .LBB5_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB5_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v16 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v15 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v13 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v11 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v7 |
| ; GCN-NEXT: v_or_b32_e32 v0, v14, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v12, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v10, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v6, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v5, v4 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB5_2 |
| ; GCN-NEXT: .LBB5_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v16 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v12 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8 |
| ; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9 |
| ; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6 |
| ; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v2, v8, v4 |
| ; GCN-NEXT: v_or_b32_e32 v3, v6, v9 |
| ; GCN-NEXT: v_or_b32_e32 v4, v5, v7 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v10f16_to_v5i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB5_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v5, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v6, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v4, 0x200, v4 |
| ; VI-NEXT: v_or_b32_e32 v4, v4, v6 |
| ; VI-NEXT: v_add_f16_sdwa v6, v3, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v3, 0x200, v3 |
| ; VI-NEXT: v_or_b32_e32 v3, v3, v6 |
| ; VI-NEXT: v_add_f16_sdwa v6, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v2, 0x200, v2 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v6 |
| ; VI-NEXT: v_add_f16_sdwa v6, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v5, v0, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v6 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v5 |
| ; VI-NEXT: .LBB5_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v10f16_to_v5i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v10f16_to_v5i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <10 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <10 x half> %a1 to <5 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <10 x half> %a to <5 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <5 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <5 x i32> %phi |
| } |
| |
| define <10 x i16> @bitcast_v5f32_to_v10i16(<5 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v5f32_to_v10i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v8, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v2, v1 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB6_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB6_4 |
| ; GCN-NEXT: .LBB6_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB6_3: ; %cmp.false |
| ; GCN-NEXT: v_alignbit_b32 v9, s4, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB6_2 |
| ; GCN-NEXT: .LBB6_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, s4, v8, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v5f32_to_v10i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; VI-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v5f32_to_v10i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v5f32_to_v10i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3 |
| ; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1 |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <5 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <5 x float> %a1 to <10 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <5 x float> %a to <10 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <10 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <10 x i16> %phi |
| } |
| |
| define <5 x float> @bitcast_v10i16_to_v5f32(<10 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v10i16_to_v5f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v13, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v12, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v11, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB7_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB7_4 |
| ; GCN-NEXT: .LBB7_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB7_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v11 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v12 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v13 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v8 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v10 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v14 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v5 |
| ; GCN-NEXT: v_or_b32_e32 v3, v3, v7 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v9 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB7_2 |
| ; GCN-NEXT: .LBB7_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v11 |
| ; GCN-NEXT: s_mov_b32 s6, 0x30000 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v12 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v13 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v8 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_or_b32_e32 v0, v10, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v14, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v5, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v7, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v9, v4 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v10i16_to_v5f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB7_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v6, 3 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v4 |
| ; VI-NEXT: v_add_u16_sdwa v4, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v4, v5, v4 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v3 |
| ; VI-NEXT: v_add_u16_sdwa v3, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v3, v5, v3 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v2 |
| ; VI-NEXT: v_add_u16_sdwa v2, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v5, v2 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v1 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v5, v1 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v5, v0 |
| ; VI-NEXT: .LBB7_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v10i16_to_v5f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v10i16_to_v5f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <10 x i16> %a, splat (i16 3) |
| %a2 = bitcast <10 x i16> %a1 to <5 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <10 x i16> %a to <5 x float> |
| br label %end |
| |
| end: |
| %phi = phi <5 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <5 x float> %phi |
| } |
| |
| define <10 x half> @bitcast_v5f32_to_v10f16(<5 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v5f32_to_v10f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v14, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v13, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v12, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v11, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v10, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB8_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB8_4 |
| ; GCN-NEXT: .LBB8_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB8_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v14 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v13 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v12 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v11 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v12 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v16 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v10 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB8_2 |
| ; GCN-NEXT: .LBB8_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v1, 1.0, v10 |
| ; GCN-NEXT: v_add_f32_e32 v3, 1.0, v11 |
| ; GCN-NEXT: v_add_f32_e32 v5, 1.0, v12 |
| ; GCN-NEXT: v_add_f32_e32 v7, 1.0, v13 |
| ; GCN-NEXT: v_add_f32_e32 v9, 1.0, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v5f32_to_v10f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; VI-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v5f32_to_v10f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v5f32_to_v10f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3 |
| ; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1 |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <5 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <5 x float> %a1 to <10 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <5 x float> %a to <10 x half> |
| br label %end |
| |
| end: |
| %phi = phi <10 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <10 x half> %phi |
| } |
| |
| define <5 x float> @bitcast_v10f16_to_v5f32(<10 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v10f16_to_v5f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v11, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v8 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB9_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB9_4 |
| ; GCN-NEXT: .LBB9_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB9_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v16 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v15 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v13 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v11 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v7 |
| ; GCN-NEXT: v_or_b32_e32 v0, v14, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v12, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v10, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v6, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v5, v4 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB9_2 |
| ; GCN-NEXT: .LBB9_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v16 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v12 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8 |
| ; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9 |
| ; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6 |
| ; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v2, v8, v4 |
| ; GCN-NEXT: v_or_b32_e32 v3, v6, v9 |
| ; GCN-NEXT: v_or_b32_e32 v4, v5, v7 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v10f16_to_v5f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB9_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v5, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v6, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v4, 0x200, v4 |
| ; VI-NEXT: v_or_b32_e32 v4, v4, v6 |
| ; VI-NEXT: v_add_f16_sdwa v6, v3, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v3, 0x200, v3 |
| ; VI-NEXT: v_or_b32_e32 v3, v3, v6 |
| ; VI-NEXT: v_add_f16_sdwa v6, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v2, 0x200, v2 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v6 |
| ; VI-NEXT: v_add_f16_sdwa v6, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v5, v0, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v6 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v5 |
| ; VI-NEXT: .LBB9_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v10f16_to_v5f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v10f16_to_v5f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <10 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <10 x half> %a1 to <5 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <10 x half> %a to <5 x float> |
| br label %end |
| |
| end: |
| %phi = phi <5 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <5 x float> %phi |
| } |
| |
| define <10 x half> @bitcast_v10i16_to_v10f16(<10 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v10i16_to_v10f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v19, v9 |
| ; GCN-NEXT: v_mov_b32_e32 v18, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v17, v7 |
| ; GCN-NEXT: v_mov_b32_e32 v16, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v15, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v14, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v13, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v12, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v11, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v20, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB10_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB10_4 |
| ; GCN-NEXT: .LBB10_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB10_3: ; %cmp.false |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v20 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v12 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v16 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v18 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v19 |
| ; GCN-NEXT: ; implicit-def: $vgpr20 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB10_2 |
| ; GCN-NEXT: .LBB10_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v19 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v18 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v17 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v16 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v15 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v14 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v13 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v12 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v11 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v20 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v10i16_to_v10f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB10_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v5, 3 |
| ; VI-NEXT: v_add_u16_sdwa v6, v0, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v7, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v8, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v9, v3, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v5, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v4, 3, v4 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v3 |
| ; VI-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v1 |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v0 |
| ; VI-NEXT: v_or_b32_e32 v4, v4, v5 |
| ; VI-NEXT: v_or_b32_e32 v3, v3, v9 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v8 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v7 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v6 |
| ; VI-NEXT: .LBB10_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v10i16_to_v10f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v10i16_to_v10f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <10 x i16> %a, splat (i16 3) |
| %a2 = bitcast <10 x i16> %a1 to <10 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <10 x i16> %a to <10 x half> |
| br label %end |
| |
| end: |
| %phi = phi <10 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <10 x half> %phi |
| } |
| |
| define <10 x i16> @bitcast_v10f16_to_v10i16(<10 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v10f16_to_v10i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB11_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9 |
| ; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8 |
| ; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7 |
| ; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v3 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v5 |
| ; GCN-NEXT: v_or_b32_e32 v8, v8, v10 |
| ; GCN-NEXT: v_or_b32_e32 v6, v6, v11 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v12 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v5, 16 |
| ; GCN-NEXT: .LBB11_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v10f16_to_v10i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB11_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v6, 0x200 |
| ; VI-NEXT: v_add_f16_e32 v5, 0x200, v0 |
| ; VI-NEXT: v_add_f16_sdwa v0, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v7, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v1, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v8, 0x200, v2 |
| ; VI-NEXT: v_add_f16_sdwa v2, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v9, 0x200, v3 |
| ; VI-NEXT: v_add_f16_sdwa v3, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v10, 0x200, v4 |
| ; VI-NEXT: v_add_f16_sdwa v4, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v4, v10, v4 |
| ; VI-NEXT: v_or_b32_e32 v3, v9, v3 |
| ; VI-NEXT: v_or_b32_e32 v2, v8, v2 |
| ; VI-NEXT: v_or_b32_e32 v1, v7, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, v5, v0 |
| ; VI-NEXT: .LBB11_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v10f16_to_v10i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v10f16_to_v10i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <10 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <10 x half> %a1 to <10 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <10 x half> %a to <10 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <10 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <10 x i16> %phi |
| } |
