llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s

# Should create an additional LSL to zero the lanes as the DstReg is not unique

--- |
  define <vscale x 8 x i16> @bic_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a){
    %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
    %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a_z, <vscale x 8 x i16> %a_z)
    ret <vscale x 8 x i16> %out
  }

  declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
...
---
name:            bic_i16_zero
alignment:       4
tracksRegLiveness: true
tracksDebugUserValues: true
registers:       []
liveins:
  - { reg: '$p0', virtual-reg: '' }
  - { reg: '$z0', virtual-reg: '' }
body:             |
  bb.0 (%ir-block.0):
    liveins: $p0, $z0

    ; CHECK-LABEL: name: bic_i16_zero
    ; CHECK: liveins: $p0, $z0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $b0_hi, implicit-def $h0_hi, implicit-def $s0_hi, implicit-def $d0_hi, implicit-def $q0_hi, implicit killed $p0, implicit $z0 {
    ; CHECK-NEXT:   $z0 = MOVPRFX_ZPzZ_H $p0, $z0
    ; CHECK-NEXT:   $z0 = LSL_ZPmI_H killed renamable $p0, internal $z0, 0
    ; CHECK-NEXT:   $z0 = BIC_ZPmZ_H killed renamable $p0, internal killed $z0, internal killed renamable $z0
    ; CHECK-NEXT: }
    ; CHECK-NEXT: RET undef $lr, implicit $z0
    renamable $z0 = BIC_ZPZZ_H_ZERO killed renamable $p0, killed renamable $z0, killed renamable $z0
    RET_ReallyLR implicit $z0
...