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fuchsia / third_party / llvm-project / refs/heads/upstream/release/2.4.x / . / llvm / test / TableGen / IntBitInit.td
blob: b949bfea7b13f846e4400ebade597f1ff6da7a61 [file] [log] [blame] [edit]
// RUN: tblgen %s
def {
bit A = 1;
int B = A;
}